8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.
- Eight interrupt request input per chip
- Up to 64 interrupt request inputs per system
- Edge or level triggered interrupt request inputs
- Individually maskable interrupt requests
- Programmable interrupt request priority orders
- Polling operation capability
- Extended mode with cascade connection of external interrupts
- Supports Slave mode in extended mode
- Can be used to assign priority levels to interrupt outputs
- Allows cascading of multiple interrupts
- Compatible with 8259A and uPD71059
- Two modes of operation make the controller compatible with 8080/85 and 8086/88/286 microprocessors
- Microcomputer system with I/O devices are serviced with efficient manner by using iW-8259A interrupt controller
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