The digital receiver module has eight independent output channels of digital down-conversion (DDC) embedded in Xilinx Virtex-6 FPGA. As a flexible front-end receiver, this module implements the frequency translation and channelization for the IF band signal as the FPGA firmware.
The firmware is implemented on the Xilinx Virtex-6 SX315T2 FPGA and consumes about 30% of the slice registers. The firmware is an optional item available for customizing the DDC project to include more features and processing capability after IP-DDC8i core.
The optional firmware also includes the netlist version of IP-DDC8i core and Matlab/Simulink model for IP core simulation. The Modelsim model is provided for system simulation.
- Analog input bandwidth: 400 MHz (AC coupled)
- Eight 14-bit inputs @ max 250 MHz
- On-board PLL from 0.3125 ~ 250 MHz; programmable PFD (default=100 KHz)
- Eight independent 16-bit DDC channels
- DDC max channel bandwidth up-to 62.5 MHz
- DDC outputs SNR >60 dB; SFDR >76 dB
- Independent tuning from DC ~ 125 MHz; resolution 0.0582 Hz @ 250 MHz sampling rate
- Independent decimation range from 4 to 256
- Programmable 20 tap CFIR (18-bit)
- Programmable 80 tap PFIR (18-bit)
- DDC Overflow indicator
- DDC reprogramming, enable/disable on-the-fly
- Built-in spectrum inversion for under-sampling
- Synchronous timestamps with internal 1 sec timer or external PPS signal
- Embedded power meter (-44 dBm ~ 8 dBm)
- 32 digital-IO bits
- Applications include Digital Receivers, Spectrum
- Analysis, and Software Definded Radio.
- X6-250M Virtex-6 FPGA Card, part #80279-9-L) bit file, application software, and manual (88011) . Optional adapters, eInstrument chassis