The UWB receiver module has two channels of digital down-conversion (DDC) embedded in Xilinx Virtex-6 FPGA. As a flexible front-end receiver, this module implements the frequency translation and channelization for the IF band signal as the FPGA firmware.
The firmware is implemented on the Xilinx Virtex-6 LX240T1 FPGA and consumes about 19% of the slice registers. The firmware is an optional item available for customizing the DDC project to include more features and processing capability after IP-POLY/4 core.
The optional firmware also includes the netlist version of IP-POLY/4 core and Matlab/Simulink model for IP core simulation. The Modelsim model is provided for system simulation.
- Analog input bandwidth: 2 GHz (AC coupled)
- Two 12-bit inputs @ max 1.2 GHz
- On-board PLL from 1.15 ~ 1.325 GHz
- Two independent 16-bit DDC channels
- DDC max channel bandwidth up-to 300 MHz
- Independent tuning from DC ~ 600 MHz; resolution 0.0349 Hz @ 1.2 GHz sampling rate
- Independent decimation range from 4 to 32
- Programmable 80 taps polyphase filter (18-bit)
- DDC Overflow indicator
- 32 digital-IO b
- Applications include digital Reciers, Spectrum Analysis and Software Defined
- Part #90420-0 X6-GSPS module (80264-7-L0); bit file, application software, and manual (88031). IP core for single channel DDC for A/D sampling rate up-to 2 GHz on Xilinx Virtex-6 FPGA
- (Netlist version); include custom project files for the UWB receiver.
- Optional eInstrument and VPX chassis