32-bit RISC processor: Configurable, small size, embedded performance

Google TV Devices with Vivante GPU Cores Ready for Android Jelly Bean Update
Ultra-Low Latency H.264 Video Encoding Now Available from CAST
Automated ECO Flow for overall cycle time reduction
SoC Interconnect Verification Challenge
The Power of Developing Hardware and Software in Parallel
Enpirion's Value is Not Necessarily in IP
Industry's First Demo of USB 3.0 SSIC and MIPI M-PHY Passing USB Compliance Tests
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MIPI LLI Webinar on EE Times, Wednesday, 27 JuneArteris Connected Blog - Kurt ShulerJun. 25, 2012 |
Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.
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