Cadence today (June 16, 2014) announced the completion of its acquisition of Jasper Design Automation, a leading provider and pioneer of formal analysis and verification tools for IP and system-on-chip (SoC) development. The acquisition allows Cadence to expand an already broad functional verification offering with the Cadence® System Development Suite, and it expands Cadence's formal portfolio just as that technology is coming into mainstream adoption.
While simulation generates directed and random stimulus to devices under test, formal analysis—generally done at the block level, and increasingly at the SoC level for specific tasks—provides a mathematical proof that determines whether a given behavior will always or never occur. Formal analysis is fast and exhaustive, but it needs to be guided to focus on issues related to how the design will be used. Recently, Cadence and other providers have offered "semi-formal" tools that combine both simulation and formal analysis, and both Jasper and Cadence have been delivering formal "apps" for specific verification issues.
Formal verification is a broader term that also includes formal equivalency checking, which compares two netlists (such as before and after synthesis) to ensure that netlists are functionally equivalent. Although Jasper is best known for formal analysis, the company recently developed a sequential formal equivalence checking capability. Sequential checking can verify an RTL netlist generated by high-level synthesis, and it also can verify that low-power and performance optimizations don't impact functionality.
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