FinFET transistors promise enormous power and performance advantages at process nodes below 20nm, but how will they impact IC design? If you're a digital designer, not much changes - but if you're a custom/analog designer, there's a lot to learn, according to panelists at the recent Design Automation Conference (DAC 2014) in San Francisco.
Titled "FinFET and IC Design: Mountain or Mole HIll?", the panel was moderated by Jamil Kawa of Synopsys, and it featured these panelists (listed in the order of their opening presentations):
- Richard Rouse, principal technologist, Microsoft
- Hugh McIntyre, principal member of technical staff, AMD
- Jean-Marie Brunet, product marketing director, Mentor Graphics
- Wilbur Luo, senior group director for custom IC and simulation, Cadence
Kawa opened the panel by noting that Intel's 22nm "tri-gate" (FinFET) announcement three years ago opened the floodgates for FinFET technology development at 16nm and 14nm. Semiconductor companies are looking to FinFETs as a way of continuing the scaling promised by Moore's Law. "Has design with FinFETs been disruptive, or is it business as usual?" he asked the panelists. Here are some of their responses.
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