Industry Expert Blogs

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of low-power servers and high-performance mobile devices. However, sophisticated interconnects have to be highly configurable, which creates unique challenges for SoC integrators and verification engineers. Seemingly minor variations in the configuration of these interconnects can introduce unintended bottlenecks that degrade SoC performance. To aid SoC developers, Cadence provides an integrated solution for interconnect verification and performance analysis. The solution includes the Cadence Interconnect Validator (discussed in this post) and Cadence Interconnect Workbench (discussed in the future posts).

Click here to read more ...