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	Exhibition		Program Committee		Best IP Awards 2007

System-on-Chip (SoC) design is increasingly an intellectual property (IP) assembly and integration task. The design productivity advantage of this approach is clear, but what about verification productivity? SoC verification continues to consume up to 70% of the total engineering effort, with significant verification effort dedicated to verifying both internal and third-party IP. And it often still fails to prevent silicon respins. The result? Increased time to market and reduced product profitability. To realize the potential quality and productivity gains of IP re-use, the industry needs innovations in verification that can efficiently achieve significantly higher levels of IP quality – levels that incremental improvements in established verification methodologies have not so far delivered. The panelists – IDMs, Infineon Technologies and ST Mircoelectronics, and EDA companies, Cadence, Certess and OneSpin Solutions – will share their experience and vision of the significant technology and methodology improvements that can make “highest quality IP” a reality.

Chairperson:

Peggy Aycinena Editor EDA Confidential

Panelists:

		Eric Panu R&D Group Director of Verification Methodology and VIP Cadence
	Erik Panu, Group Director of Verification Methodology and Verification IP, oversees and is responsible for the Universal Verification Component and Incisive Plan-To-Closure Methodology product development. Between 1993-1997, Mr. Panu worked at Compaq Computer on an internal verification tool and methodology as well as their proliferation within the company. In 1997 he joined Verisity where he co-developed and deployed Verisity s initial verification sales process, directed and managed US East coast and Silicon Valley sales/field territories and contributed to the Verification Advisor and e Reuse Methodology (eRM). Since 2004 Mr. Panu works for Cadence. Mr. Pnau holds a Bachelor of Science and Master of Science degree in Computer Science from University of Georgia.
		Mark Hampton CTO Certess
	Mark Hampton, Co-founder and Chief Technology Officier of Certess Inc., is responsible for product direction at Certess and leads research in mutation analysis for hardware and software systems. Before co-founding Certess Inc., Mr. Hampton was responsible for digital ASIC design and verification at Tait Electronics (New Zealand), Parthus (Ireland), Qualis (France). Mr. Hampton holds a 1st class honors degree in Electrical and Electronic Engineering from the University of Auckland, New Zealand.
		Olivier Haller STMicroelectronics
	Olivier Haller is the manager of the Design Verification Team in the Functional Verification Group at STMicrelecronics. He is responsible for the definition and deployment of dynamic verification methodologies at ST, including support for key ST projects. Mr. Haller started his carreer at ST in 1998 as digital designer for wireless products. In 2000 he pursued functional verification as member of the CAD support team, introducing coverage-driven verification techniques. Since 2004 he is leading the dynamic verification team in ST s central verification group where he has been pioneering the introduction of functional qualification within ST to qualify IPs and improve verification environements. Mr. Haller is graduated from Grandes Ecoles d ingénieur en électronique in Grenoble and holds a joint ENSERG/ENSIMAG engineering degree in electronics and computer science.
		Steve Neill Managing Director Infineon UK ltd.
	Steve Neill, VP Bristol Design Centre and Managing Director Infineon UK Ltd., is responsible for the design and verification of the TriCore micro-controller, Peripheral Control Processor and related systems peripherals. As Managing Director of IFX UK Ltd he oversees the UK operations. Mr. Neill started work for International Computers Ltd back in 1982, joined Inmos in 1984 and then STM through acquisition of Inmos in 1989. He joined Infineon in 1999. He is the Chairman of the National Microelectronics Institute, a UK industry run organisation. His experience covers both process and processor development during which time he managed numerous processor developments. Mr. Neill holds a BSc in Electronics, University of Hull
		Dr. Wolfram Büttner CTO OneSpin Solutions
	Dr. Wolfram Buettner, Managing Director, Founder and CTO of OneSpin Solutions, defines the company s technology roadmap and leads product development. Mr. Buettner began his business career at the Corporate Research Labs of Siemens, where he established fundamental research on the design and verification of hardware and software. He served for more than a decade as Senior Director of the Research Lab s Design Automation Department, where the advanced Circuit Verification Environment (CVE) originated that later formed the basis of OneSpin Solutions. Mr. Buettner holds a Ph.D. in mathematics from Tulane University, Louisiana, USA, a post-doctoral degree in mathematics from the Technical University of Darmstadt, Germany; and a post-doctoral degree in computer science from the Technical University of Kaiserslautern, Germany. Based on his work in automated reasoning, he was awarded the title of Professor by the Computer Science Department of the Technical University of Kaiserslautern.