Design Reuse

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Exhibition Program Committee Best IP Awards 2007
Panel: Is networking the solution for interconnect design closure? (Dec. 5, 16:30-17:45)

In several application domains, such as multi-media processing, the communication requirements between the cores in Systems-on-Chips (SoCs) is rapidly increasing. In the future, with the integration of many applications onto a single device and with increased processing speed of cores, the bandwidth demands will scale up to much larger values. The SoC performance will be increasingly determined by the ability of the communication infrastructure to efficiently accommodate the communication needs of the integrated computation resources. In fact, the system architecture design paradigm is already progressively shifting from computation-centric to communication-centric. To effectively tackle the interconnect design complexity of current and future SoCs, a micro-networks based interconnect architecture, Networks on Chip (NoC), has recently emerged. In this panel, we will discuss how the NoC paradigm can help reduce the design efforts and achieve design closure, satisfying the ever increasing communication requirements of SoCs.

Chairperson:
   

Srinivasan Murali
Ecole Polytechnique Federale de Lausanne
Dr. Srinivasan Murali is a research scientist at the Integrated Systems Lab at the Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland. He received the MS and PhD degrees in Electrical Engineering from Stanford Univeristy in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chip IPs. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium) as session/publicity chair and is a reviewer for many leading conferences and journals. He recently received a best paper award in the DATE 2005 conference for his work on interconnect architecture design and he has over 25 publications in this field.


Panelists:
   

John Bainbridge
Founder and Chief Technology Officer
Silistix
Dr. Bainbridge is a founder and the Chief Technology Officer at Silistix. Prior to founding Silistix, John Bainbridge was a research fellow in the Department of Computer Science at the University of Manchester, UK. He received an MEng degree in Electronic Systems Engineering in 1996 and his PhD in Computer Science from the University of Manchester University in 2001 for work on Asynchronous System-on-Chip Interconnect - CHAIN. CHAIN is the foundation of the company s interconnect fabric technology. His thesis, winner of the 2001 British Computer Society/CPHC Distinguished Dissertation Competition, described the design of the MARBLE asynchronous system bus used in the Amulet3i subsystem on the DRACO communications chip.

   

Marcello Coppola
STMicroelectronics
Dr. Coppola is the head of the Grenoble research lab within the Advanced System Technology department at STMicroelectronics-Grenoble. His research interests include discrete event simulation, networks on chip and modeling of multiprocessor systems on chip. Coppola received a Laurea degree in computer science from the University of Pisa, Italy.

   

Philippe di Crescenzo
Product Marketing Director
Arteris
Crescenzo is the product marketing director of Arteris.

   

Milos Krstic
IHP Microelectronics