In SoC design, the validation of hardware, software, and firmware can be achieved on a common prototypes. This panel will focus on what s required to support this purpose in a prototyping process including co-emulation, IP encryption, integration of hard/soft IPs and debugging features.
Current leading edge FPGAs contain complex IPs such as RISC processors, high speed SERDES and DSP blocks. In addition they support multiple high-speed I/O interfaces to implement many generation of bus interfaces (eg. PCI Express) and memory interfaces (eg. DDR SDRAM controller). These features make new breed of FPGAs ideal for implementing FPGA based SoC solutions or validating SoC functionality.
This FPGA-based prototyping approach gives designers considerable flexibility to use IP from third party vendors and allow them to mix their logic on the same silicon before they go into high volume ASICs or FPGAs. We expect to gather in this panel major IP/Prototyping providers (eg. Cadence, Mentor) and SoC design companies (eg. Bull, STm, Thalès).
Huy-Nam Nguyen Head of System Modelling and Verification Service
Bull / METASymbiose
NGUYEN Huy-Nam is actually responsible for Formal Verification, High-Level Modelling and Hardware Prototyping at Bull S.A.S.
Previously, he held various R&D positions at Bull S.A.S. where he developed CAD solutions for ASIC design including
Hardware Modelling, Functional Simulation , Logic Synthesis and Formal Verification. Huy-Nam graduated Engineer from l Ecole Nationale Supérieure des Mines de Paris in 1977 and received the Docteur-Ingenieur degree in Applied Mathematics from Université Paris-IX in 1982.
Luc BURGUN President and CEO EVE
- President and CEO of EVE
- President of the supervisory board of Cofluent Design
Dr. Luc Burgun is co-founder of EVE and has 18 years of experience in CAD development and digital system design.
Prior to founding EVE, Luc was the R&D Director at Meta Systems, a wholly owned subsidiary of Mentor Graphics, specializing in hardware emulation systems. He has published numerous articles at international technical conferences
and has been granted six patents on accelerated verification. Luc has also taught VLSI design and holds a Ph.D degree
in Computer Science from the University of Paris-Jussieu, France.
Syed Zahid Ahmed LIRMM / Menta
Syed Zahid AHMED is currently a researcher between LIRMM and Menta. At Menta he is working as Technical manager and is in charge of eFPGA architecture explorations. At LIRMM his research includes MPSoC and NoC. Prior to joining Menta he spent almost one year in Fraunhofer Institute and LIRMM for research related with FPGAs and NoC. He did BSEE with honours from U.E.T. Taxila, Pakistan in 2002, MSEE from TU-Darmstadt Germany in 2006. He has more then three years of research oriented multinational work experience in areas like Chip design, Reconfigurable architectures, FPGA architecture design & prototyping, NoC and embedded systems.
Lars-Eric Lundgren General Manager of Synplicity Hardware Platforms Group Synplicity
Lars-Eric Lundgren General Manager of Synplicity Hardware Platforms Group
Lars-Eric Lundgren joined Synplicity in June 2007 with the acquisition of the Swedish ASIC Prototyping Company; HARDI Electronics AB. Mr. Lundgren is responsible for all hardware development at Synplicity, including the current product line of HAPS (High-performance ASIC Prototyping System) and any future hardware products. The Hardware Platforms Group is located in Lund, Sweden.
Mr. Lundgren co-founded HARDI Electronics AB in 1987 and has 20 years of experience as President and CEO of the company. In the beginning of the company’s history, Mr. Lundgren worked as a hardware design engineer on various ASIC and FPGA design projects. He trained hundreds of engineers in Structured Electronic Design and acted as a reseller of EDA software tools like ModelSim and Synplify. HARDI represented Synplicity in the Nordic region from 1995 to 2003 and the use and sale of the Synplicity Certify software lead to the development of the HAPS ASIC prototyping hardware. In 2003 HARDI focused on hardware and Mr. Lundgren worked with setting up the world wide sales organization. From 2003 to 2006 sales grew by over 100% every year.
Prior to founding HARDI, Mr. Lundgren worked at several Swedish companies as designer and team leader with the task of designing boards, ASICs and FPGAs. Mr Lundgren was well known in Sweden as an advocate for promoting new design techniques. This was one reason why HARDI promoted VHDL very early. The Company developed the world’s first VHDL synthesis tool and trained over 1000 engineers in VHDL.
Eric Selosse Mentor Graphics
Helena Krupnova STmicroelectronics
- Helena Krupnova
Received a PhD in Computer Science from Institut National Polytechnique
de Grenoble in 1999 in the domain of multi-FPGA partitioning and prototyping.
Since 2000 - leading the prototyping activity within the central ST team:
Functional Verification Group (FVG) belonging to the IP & Design service,
PSS/MMC, ST Microelectronics, Grenoble. Has been in charge of prototyping
of more than 10 multi-million gate ST SoC using Aptix and EVE technologies.
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