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DAY 1: December 3, 2008
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AUDITORIUM
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07:00 |
Registration
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08:45 |
Welcome
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09:00 |
Keynote Talk: IP Reuse leading the way of Enterprise level IP management
 By David Yoon
Sr. Manager of IP Management
Cisco systems
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09:30 |
Keynote Talk: IP management platforms: A success story
 By Gabriele Saucier
CEO
Design And Reuse
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10:00 |
Break
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10:30 |
Keynote Talk: SoC/IP Market Overview and Outlook
 By Jim Tully
Vice President, Chief of Research Semiconductors
Gartner
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11:00
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Keynote Talk: Feeding the Beasts: Optimized Shared Memory Solutions for MPSoCs
 By Drew Wingard
CTO
Sonics
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11:30 |
Keynote Talk: Research programs and model of collaboration: the Silicon Sea belt program
 By Eisaku Ohtsuru
R&D Managing Director
Fukuoka Industry, Science & Technology Foundation
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12:00
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Lunch
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AUDITORIUM
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ROOM
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ROOM
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ROOM
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13:00 |
Panel: When will the Virtual Software Platform hook up to the Virtual Hardware Platform ?
Moderator:
 Pierre Bricaud
Director, IP R&D Solutions Group
Synopsys
Panelists:
- Markus Willems, Senior Product Marketing Manager, Synopsys
- Peter Flake, Elda Technology
- Jakob Engblom, Technical Marketing Manager , Virtutech
- Loic Le Toumelin , Texas Instruments
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13:00 |
Session: Standard & Integration
Chairman: David Yoon, Sr. Manager of IP Management (Cisco systems )
-"The Value of High Quality IP-XACT XML" by Marc van Hintum1 Hintum from NXP Semiconductors & Paul Williams from Mentor Graphics
-"Assisted creation and refinement of transactional level specifications based on IP-XACT" by Nicolas Laug, Guy Bois & Marc-André Cantin from École Polytechnique de Montréal
-"Refactoring to Prepare RTL for Reuse" by Steve Haynal from Intel Corporation
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13:00
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Session: Configurable Systems
Chairman: Francois Kleitz, Silicon and IP Providers Technical Manager (Alcatel Lucent)
-"Tailored SoC building using reconfigurable IP blocks" by Lodewijk Smit, Gerard Rauwerda, Jochem Rutgers, Maciej Portalski & Reinier Kuipers from Recore Systems
-"CUSTOMIZABLE SoC SPEAr® FROM STMicroelectronics SOLVING TIME TO MARKET ISSUES" by Matteo Mazzola, Bruno Cristofoli, Henry Le Henaff & Alain Pasteur from ST
-"Enabling Secure Integration of Multiple IP Cores in the Same FPGA" by Bassel Soudan from University of Sharjah, Wael Adi from Technical University of Braunschweig, Abdulrahman Hanoun from Technical University of Hamburg
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13:00
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Session: IP Design (1)
Chairman: Paolo Pezzati (Cadence)
-"Practical Design and Implementation of a Configurable DDR2 PHY" by Lior Amarilio from ChipX 
-"A generalized waveform synthesis mechanism for software radio" by Maurizio Colizza & Fabio Graziosi from Westaquila, Claudia Rinaldi from University of L'Aquila
-"DDR SDRAM Controller IP Designed for Reuse" by Alexsandro Bonatto, André Soares & Altamiro Susin from UFRGS
-"Stochastic Computation applied to the design of Error Correcting Decoders" by Gordon Harling from WideSail Technologies, Warren Gross & Shie Mannor from McGill University
-"A multi-purpose Digital Controlled Potentiometer IP-Core for nano-scale Integration " by Reimund Wittmann, Ralf Kakerow & Harald Bothe from IP Gen Rechte GmbH, Werner Schardein from University of Applied Sciences and Arts, Dortmund
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14:30
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Panel: IP vision for FPGA : Do complex FPGA designs rely on the use of vendor-created and third-party IPs ?
Moderator:
 Dick Selwood
Embedded Technology Journal
Panelists:
- Francois Kleitz, Silicon and IP Providers Technical Manager, Alcatel Lucent
- Stuart Nisbet, Director of IP Development , Xilinx
- Mark Dickinson, Vice President of Altera's European Technology Cente , Altera
- Tom Moore, Director, IP Development, Actel
- Ralph Morgan, VP of Engineering for Digital IP, Synopsys
- Gabriele Saucier, CEO, Design And Reuse
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14:30 |
Session: High Level Modeling (1)
Chairman: Laurent Ducousso , STMicro
-"An UML-driven Interface Generation Approach for SoC Design with Synthesizable SystemC Code Generation" by André Aziz, Francielle Santos, Daniele Santos, Millena Gomes & Edna Barros from Informatics Center. Federal University of Pernambuco
-"Launchers Avionic Chains modelling based on SystemC for early Hardware-Software breakdown and Interfaces definition" by Arnaud Stransky & Laurent Chevalier from Astrium
-"Advances in SoC and Processor Modeling Methodologies" by Syed Saif Abrar from NXP
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14:30
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Session: SoC Design and Reuse (2)
Chairman: Kunihiro Asada (University of Tokyo)
-"IP-based toolbox for digital signal processing reuse: Application to Real-time Spike sorting" by Timothée Levi, Jean-François Bêche, Stéphane Bonnet & Régis Guillemaud from CEA-LETI, DTBS/STD/LE2S
-"A Cost-Optimized Set-Top Box Architecture" by Stuart Ryan from STMicroelectronics, Andrew Jones from STMicroelectronics, Robert Deaves from STMicroelectronics
-"Migrating from SPI 4.2 to SPI 5 IP Core – Architectural Changes and Re-usability" by Kaushal Buch from eInfochips Ltd.
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14:30
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Session: IP Design (2)
Chairman: Kunihiko Tsuboi (STARC)
-"uBIP: A Simplified Microcontroller Architecture for Education in Embedded Systems Design " by Maicon PEREIRA & Cesar ZEFERINO from UNIVALI
-"A 1-10Gbps SerDes IP in 65nm CMOS Technology" by Afshin Rezayee, Angus McLaren, Saman Sadr, Robert Wang & Mehrdad Ramezani from SnowbushIP
-"Debug and testability features for multi-protocol 10G SerDes" by Claude Gauthier, Shaishav Desai & Sanjay Dabral from Prism Circuits
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16:00
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Break
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Break
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Break
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Break
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16:30
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Panel: Easy Third-Party IP Integration - Fact or Fiction?
Moderator:
Jim Tully
VP Distinguished Analyst
Gartner
Panelists:
- Xerxes Wania, President and Chief Executive Officer, Sidense
- Ralph Morgan, Senior Director of Engineering , Synopsys
- Christophe Frey, ARM
- Ange Aznar, Director of Semiconductor IP Engineering, Wipro NewLogic
- Cesar Martin-Perez , Vice President, European Operations, MIPS Technologies
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16:30
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Session: High Level Modeling (2)
Chairman: Laurent Ducousso , STMicro
-"How high-level synthesis can raise the efficiency of design reuse" by Thomas Bollaert from Mentor Graphics Corporation
-"UML-based Design of a JPEG-LS IP via Axilica FalconML" by Scott Moyers, Robert Thomson, Vassilios Chouliaras & David Mulvaney from Axilica
-"SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology" by Gaurav Kumar-Verma & Rudra Mukherjee from Mentor Graphics
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16:30
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Session: SoC Design and Reuse (1)
Chairman: Ian Phillips (ARM)
-"Embedded Software Architecture Specification Developments in Support of SoC Design and Re-use" by Robert Deaves, Andrew Jones & Stuart Ryan from STMicroelectronics
-"SoC IP Interfaces and Infrastructure: A Hybrid Approach" by Cary Robins & Shannon Hill from ChipWrights
-"A Re-Usable Level 2 cache Architecture" by Andrew Jones, Mark Hill, Mark Beaumont, James Pascoe & Stuart Ryan from STMicroelectronics
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16:30 |
Seminar: IP-XACT Users’ Group First European Meeting
Organizer:
 Adam Morawiec
ECSI
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17:30
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Session: Business Model
Chairman: Peter Hirt (STMicroelectronics)
-"from IP re-use to Open Innovation: a new industry trend" by Patrick Blouet from STMicroelectronics
-"Break-up of the Fabless Semiconductor Model – Has the time come?" by Paul Slaby from Kaben Wireless Silicon
-"In 2010, PCIe, SATA and USB IP Market will represent $200M" by Eric Esteve from Snowbush (Consultant)
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17:30
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18:00 |
 Industry
Organizations - An Overview
Ian Mackintosh
OCP-IP
Chairman and President
 OCP-IP SLD New Generation : Using
OSCI-TLM-2.0 to Model a Real Bus Protocol at Multiple
Levels of Abstraction
Mark Burton
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18:30
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19:00
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19:00
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19:15 |
Banquet
| Join us for knowing more about French traditional
food and wine from French
regions and enjoying our friendly
community ambiance . |
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DAY 2: December 4, 2008
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AUDITORIUM
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ROOM
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ROOM
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ROOM
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09:00 |
Keynote Talk: Open Innovation Platform and IP
 By Douglas Pattulo
European Director
TSMC
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09:00
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Keynote Talk: Behavioral Indexing: A Breakthrough in Design Reuse and IP Modification
 By Kathryn Kranen
President and CEO
Jasper Design Automation
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09:00
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Seminar: Verification for Embedded Software IP
Organizer:
 Oliver Bringmann
FZI
Speaker:
- Thomas Schulz, Robert Bosch GmbH
- Djones Lettnin, University of Tübingen
- Markus Winterholer, Cadence
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09:30 |
Panel: Addressing the challenges in Power Modelling at the ESL Level
Moderator:
 Glenn Perry
G.M., ESL and HDL Design Creation
Mentor Graphics
Panelists:
- Jack Donovan , President, XtremeEDA
- Andrea Battistella, Virtual Platform Manager of Application Processor division, ST-NXP-Wireless
- Ian Phillips , ARM Fellow, ARM
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09:30 |
Session: IP Quality
-"Embedded Software IP Verification" by Markus Winterholer from Cadence Design Systems
-"Requirements for intellectual properties in safety critical airborne electronic hardware" by Pascal Pampagnin from airbus
-"ipPROCESS: A Usage of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi Project Environment" by Francielle Santos, André Aziz, Daniele Santos, Millena Gomes & Edna Barros from Federal University of Pernambuco
-"Semiconductor IP Quality – A User guide" by Gerardo Nahum & Omri Raisman from Rosetta IP
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10:00 |
Break |
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10:30 |
Break
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Break
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10:30
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Seminar: Tera-Scale Architectures
Organizer:
 Huy Nam Nguyen
Bull S.A.S. / METASymbiose S.A.S.
Speaker:
- Huy Nam Nguyen, Bull S.A.S. / METASymbiose S.A.S.
- Professor Alain Greiner, UPMC/Lip6
- Sjoerd MEIJER, ACE
- Ivan MIRO-PANADES, CEA/Leti
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11:00
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Panel: SOC Configurability -- Balancing Manufacturing and R/D Costs
Moderator:
Jim Tully
Gartner
Panelists:
- Ian Phillips, ARM
- Philippe Magarshack , STMicroelectronics
- Yakov Levy , MIPS Technologies
- Dan Hillman , Transmeta
- Syed Zahid AHMED, Menta/Lirmm
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11:00 |
Session: NoC & SoC
Chairman: Srinivasan Murali, Co-founder and CTO (iNoCs)
-"A Set of VHDL IPs to Evaluate Performance of Netwoks-on-Chip" by Thiago PEREIRA & Cesar ZEFERINO from UNIVALI
-"A Twenty-four Processors System on Chip FPGA Design" by Zhoukun Wang & Hammami Omar from ENSTA ParisTech
-"Networks-on-Chip with Reprogrammable Interconnections" by Yuriy Sheynin & Elena Suvorova from Saint-Ptersburg University of Aerospace Instrumentation
-"A new Buffering Algorithm for data and commands over a high speed interconnect" by Manjunath R & Vikas Jain
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11:00
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Session: Verification (1)
Chairman: Bill Martin (Mentor Graphics)
-"Automating Protocol Compliance Verification Using Metric Driven Verification" by Erez Kovshi, Tamar Meshulum, Levent Caglar & Pete Heller from Cadence Design Systems
-"Finding out the right verification methodology for SOC verification" by Rajiv Gupta from HCL TECHNOLOGIES LTD
-"Learning Not to Fear PCI Express Compliance Using a Predictable, Metrics Driven Methodology" by Mike Bartley & Jim Hutchinson from ClearSpeed Technology Plc & Dimitry Pavlovsky & Pete Heller from Cadence Design Systems
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12:00 |
Lunch
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13:00
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Panel: “Quality of Design Flows” or “Flows for Design Quality” ?
Moderator:
 Hein Van Der Wildt
CEO
Fenix Design Automation
Panelists:
- Christoph Heer , Senior Director, Infineon
- Henrik Pallisgaard, Co-Founder and VP of Development , Nangate
- Jo Borel, ex-VP, STMicroelectronics
- Michel Tabusse, CEO, Satin IP Technologies
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13:00 |
Session: Prototyping (1)
Chairman: Helena Krupnova (STMicroelectronics)
-"A Platform for Performance Validation of memory controllers" by Ramchandra Vibhute, Manikandan Panchapakesan & Haridas V from NXP semiconductors, Bangalore
-"H.264 Baseline Encoder with ADI Blackfin DSP and Hardware Accelerators" by Anand V Kulkarni from Wipro Technologies, Bangalore, Mark Cox & Shankar Malladi from Analog Devices Inc. & Issam Nsibi from Ebsys Technology
-"Embedded software development using an interpretive instruction set simulator" by Wojciech Sakowski from Institute of Electronics, Silesian University of Technology & Łukasz Mirek & Filip Rak from Evatronix
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13:00 |
Seminar: Network on Chip
Organizer:
 Srinivasan Murali
Co-founder and CTO
iNoCs
Speaker:
- Olivier Bringman, FZI
- Antonio-Marcello Coppolla, ST microelectronics
- Srinivasan Murali , Co-founder and CTO , iNoCs
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13:00 |
Session: Verification (2)
Chairman: Thierry Pfirsch (Alcatel Lucent)
-"Generic and Automatic Specman based Verification Environment for Image Signal Processing IPs" by Abhishek Jain, Mahesh Chandra, Arnaud Deleule & Saurin Patel from STMicroelectronics
-"Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms" by Frank Schirrmeister, Sam Tennant & Markus Willems from Synopsys
-"Transactions in an OVM SystemVerilog Verification Environment" by Rich Edelman from Mentor Graphics
-"TRACE BASED APPROACH FOR UNIT LEVEL DEBUG AND VERIFICATION OF C/C++ IP MODELS" by Amit Nene & Swaminathan Ramachandran from Texas Instruments
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14:30
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Break
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14:30 |
Break
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14:30 |
Break
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14:30 |
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15:00 |
Panel: Is TLM 2.0 Truly the Panacea for Interoperability?
Moderator:
 Bill Martin
Mentor Graphics
Panelists:
- Markus Willems, OSCI Board Member , Synopsys
- Yossi Veller , ESL design technologist , Mentor Graphics
- Jack Donovan , President, XtremeEDA Corp.
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15:00 |
Session: Prototyping (2)
Chairman: Syed Zahid Ahmed (Menta/Lirmm)
-"Fast Design Productivity for Embedded Multiprocessor Through Multi-FPGA Emulation The case of a 48-way Multiprocessor with NOC " by Xinyu LI & Omar HAMMAMI from ENSTA ParisTech
-"EDA tools and Design Methodology for multi-FPGA Designing/ Prototyping" by Barun Kumar De & Shridhar Laddha from SoftJin Technologies Pvt. Ltd.
-"Developing high simulation speed VLIW processor model for software development" by Mohit Paul & Syed Saif Abrar from NXP
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15:00 |
Session: Technology Impact
Chairman: Hein Van Der Wildt, CEO (Fenix Design Automation)
-"Analog IP Integration in SoC: Challenges and Solutions" by Pankaj Singh from Infineon Technologies
-"Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes" by Dan Hillman from Transmeta Corporation
-"Comprehensive tool for on-chip ESD protection design to achieve first-time-right success" by Bart Keppens, Ilse Backers, Wim Vanhouteghem & Pieter Donck from Sarnoff Europe
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16:30 |
Cocktail
- BEST IP
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Join us for the Best IP Prizes Cocktail
and enjoy French Champagne ..
Au revoir and see you next Year |
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18:00
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