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Seminar:
IP for In-System Silicon Validation and Debug
Because complete system-level (including software) verification of a complex SoC is not feasible pre-silicon, in-system, at-speed silicon validation has become an essential step in the development of new SoCs. Hardware-software integration, operation under stress conditions, corner cases of the behavior of IP cores, robust response to unexpected inputs, digital-analog interactions, signal integrity problems, and adaptive control of temperature, voltage, and power are now standard elements of “whole system” validation methodologies. Currently, silicon validation and debug is impacted by severely limited observability (and controllability) of the internal dynamic behavior of the chip, by non-deterministic system operation, by lack of time-specific expected values, and by defects that escape the manufacturing test and are detected in system. This has become the most difficult phase of the development cycle, often requiring a third of development time and intense engineering effort.
Speakers:
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