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Status of IP and SoC
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The SoC Challenge
H. Van der Wildt , Sagantec (USA) |
SESSION
1 : Reuse Methodology
"Open Source SoC IP : The revolution
has begun" - C. Pabouctsidis, MetaFlow Technologies, (USA)
"Introducing Design Reuse : the First
Step" - M. Montefiori, A. Bramati, G. Bezzi, D. Bruno, Siemens Icn (Italy)
"A Reuse System Including Tools and
Methods for IP Management , Code Analysis and Testbench Generation" - A.
Reutter, Robert Bosch GmbH Reutlingen; J. Schneider and S. Ruelke, FhG
Dresden; T. Bohn and K. Unger, TU Chemnitz (Germany)
"An Efficient Bridging Solution Between
Working Space Management and Reuse Management System" - L. Gahnmi, O.
Chich, G. Saucier, D&R (France) |
SESSION
2 : SoC Design Platform
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SESSION
3 : IP/Core/SoC Design
"Evolution of a Soft Core Microcontroller
for Embedded Applications" K. Edwards, Mentor Graphics (UK)
"A Clock Tuning Circuit for IP Core
Integration in SoC" - Y. Elboim, A. Kolodyn, R. Ginosar, Oren, Technion
(Israël)
"Bus Data Encoding with Adaptive Code-Book
Method for Low Power IP Based Design" - S. Komatsu, M. Ikeda, K. Asada,
University of Tokyo (Japan)
"On Design and Validation of an Anti-aliased
Line Draw Engine" - B. Chowdhuri, D. Bhagatwala, ST Microelectronics
(USA)
"Designing an Image Compression System
for a Space Application, Using an IP Based Approach" - L. Baguena, J.M.
Garigue, E.Liégon, Alcatel Space Industries (France)
"Wavelet IP Core for Data Coding" -
C.
Diou, L.Torres, M. Robert, LIRMM (France)
"Design and Synthesis of a 2D Discrete
Wavelet Transform Virtual Component at Behavioral Level" - G.
Savaton, E. Casseau, E. Martin, LESTER, Université Bretagne (France) |
SESSION
4 : System Prototyping and Verification
"Design Duration and Associated Cost
of a Real Case Study in Rapid Prototyping" - M. Ferloni, G. de Blasio,
L. Gazzi, R. Gemelli, M. Pavesi, Italtel S.p.A. (Italy)
"FlexBench TM : Added Value of an Innovative
Rapid Prototyping Platform" - A. Caccia, Siscad S.r.L., Italy, A. Costoloni,
FlexTel S.p.A, Italy, P. Deroux-Dauphin, Temento S.A., France, J.P. Moreau,
Arexsys S.A., France, M. Pavesi, Italtel S.p.A., Italy, G. Sbarra, Mistel
S.p.A. (Italy)
"Rapid Prototyping Platform for Reactive
Systems with a POLIS-based HW-SW Codesign Approach" - J. Tirado, Calmell
S.A., Spain, M. Serra, Univ. De Vic, Spain, A. Portero, Q. Saiz, L. Ribas,
J. Carrabina, Univ. Barcelona (Spain)
"Adapting a Core Testbench for System-Level
Verification" - K. Edwards, Mentor Graphics (UK)
"InTime : A Multi-Tool Environment
to Ensure Timing Constraints Integrity for SoC Designs" - P.A. Nsame,
R. Grou-Svabo, Y. Savaria, Ecole Polytechnique, Montréal, Québec
"Creative Verification for Complex
System-on-Chip Designs" - R. Howarth, Ikos Systems (UK)
"Accelerated Verification of SoC Designs
Containing IP Cores" - D. Hulance, Mentor Graphics (France)
"Re-usable IP Takes Center Stage in
Rapid Prototyping & Verifying of SoC Design" - L. Rosqvist, Aptix
(USA)
"IP RTL versus IP FPGA Optimized Netlist
: Functional Equivalence" - A. Vignollet, P. Bricaud, Mentor Graphics
(France)
"Neural network prototyping approach
for localization and classification in image processing" - R. Molz,
P.M. Engel, UFRGS, BR, F.G. Mooraes, PUCRS, BR, L. Torres, M. Robert, LIRMM
(France)
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