"IP / SOC VERIFICATION" SESSION

• "Increased Verification productivity through extensive reuse" by Giles Hall from Verisity Design (UK)

• "Functional Verification of a CAN Data Layer Implementation: A Case Study" by A. Souza, J. Sabino & P. Domingues from Motorola (Brazil)

• "A Toolkit for Rapid Modeling, Analysis and Verification of SoC Designs " by R. Deaves & A. Jones from SuperH (UK)

• "System C Verification, Simulation & Emulation of Secure Digital IP" by Ken Reid from Cadence Design Systems (UK)

• "The role of Verification IP in Complex Core Design" by Saverio Fazzari from Cadence Design Systems (USA)

• "Selecting the Right Cell Library IP for Nanometer Technology" by Mike Colwell & Gene Sluss from Virage Logic (USA)

• "Mixed Signal SoC Applications" by Ron Landry from AMI Semiconductor  (USA)

• "Maximize Design Flexibility with Fast Turnaround Time while Minimizing Design Costs with Metal Programmable Libraries" by D. Sherlekar, O. Siguenza & H. Yang from Virage Logic (USA)

• "‘A la Carte’ SoCs require innovative IO management" by David Murray from Duolog Technologies (Ireland)

• "Improving Design Timing and Simplicity for Lower Cost and High Performance Multistandard Audio Decoder STA012" by M. Bosco from STMicroelectronics (Italy) & S. Bordbar & S. Tiralongo from Synopsys (Italy)

• "Hardware/Software Partitioning Methodology for Systems on Chip (SoCs) with RISC Host and Configurable Microprocessors" by S. Takagi, At. Masuda & R. Ohyama from Toshiba (Japan), H. Eichel from Toshiba Electronics Europe (Germany) & N. Matsumoto, Toshiba (Japan)

• "Dynamic Floorplanning: A Practical Method Using Relative Dependencies for Incremental Floorplanning" by H. Menager from Philips semiconductors (USA), M. Basel from Mentor Graphics (USA) & R. Kadiyala from Philips semiconductors (USA)

• "Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often" by H. Sanghavi, Tensilica (USA) & S. Leibson from Tensilica (USA)

• "A Framework for Selection of Cache Configurations for Low Power" by Z. Stamenkovic, F. Vater & Z. Dyka from IHP GmbH (Germany)

• "CoreWare® Subsystem based design" by B. Singh from LSI Logic Corporation (USA)

• "Chip level IP for Low power Single chip Wireless Transceivers" by C. Faulkner from Jennic (UK)

• "Methodology for flow integrations in a SOC design" by P. Guruswamy from Wipro (India) & H. Kwan from Texas Instruments (USA)

• "System Design Methodologies for System-on-Chip and Embedded Systems" by E. Blokken , J. Vounckx, J. Bormans, S. Vernalde & P. Wambacq from IMEC

• "An analysis and implementation of high fairness arbitration mechanism by using level-table and static priority orders in shared bus architecture" by J. Suh & H.-J. Yoo from Korea Advanced Institute of Science and Technology

• "Reliability-based Characterization of Semiconductor IP in SoC Design" by You-Pang Wei & Bill Wasserman from Legend Design Technology, Inc. (USA)

• "Variable-integration-time image sensor for wide dynamic range" by Takaya Yasuda from Tokyo University of Science(Japan) Takaya Yasuda, Takahiro Ogi & Takayuki Hamamoto from Tokyo University of Science (Japan) & Kiyoharu Aizawa from University of Tokyo (Japan)

• " Real-Time Face Detection Using Six-Segmented Rectangular Filter (SSR Filter) " by O. Sawettanusorn, Y. Senda & H. Yamauchi from Ritsumeikan University (Japan)

• "Scalable IP Core of Vector Stream Cipher" by K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan)

• " Reconfigurable Processor Device from IPFlex Inc." by T. Sato from IPFlex Inc. (Japan)

• "IP Cores for Accelerating JPEG2000" by O. Cantineau from Barco Silex (Belgium)

• "IP Core of Statistical Test Suite of FIPS PUB 140-2" by A. Hasegawa & S.-J. Kim from Communications Research Laboratory (Japan) & K. Umeno from Communications Research Laboratory and Chaos Ware Inc. (Japan)

• "Lessons learnt in IP Reuse" by C.Gendarme, F.Kleitz & I.Hrynchyshyn from Alcatel (France, Belgium), L.Ghanmi, M.Hamdoun & B.Missaoui from Design and Reuse (France), K.Benseffaj, A.Hanczakowski & M.Vandendriessche from STMicroelectronics (France)

• "VSI Alliance Quality IP Metric" by K. Werner from Mentor Graphics (USA)

• "IP Core-centric ommunications protocol" by F. Seigneret from Texas Instruments (France) & OCP-IP Specification Working Group

• "Store and Forward Fat-Tree Architecture for on-Chip Networks" by Filippo Mondinelli from University of Brescia (Italy)

• "SBAG : The on-chip STBus traffic analyzer" by Bernard Ramanadin from STMicroelectronics (France)

• "CCP: Customizable Control Processor" by Juergen Hilsberg, IBM (Switzerland)

• "Spirit Compliant Platform Design using an IP Repository" by Mark Peryer from Mentor Graphics (UK)

• "An ASIC Platform Manager" by G.Saucier, K.Skiba, Ph.Rols & Ph.Coeurdevey from Design And Reuse (France) & H.N. Nguyen from METASymbiose S.A. (France)

• "Structured ASIC Based SoC Design" by Rick Mosher from AMI Semiconductor (USA)

• "The CREC Reconfigurable Computer" by O. Cret from Technical University of Cluj-Napoca (Romania)

• "3+ Ways to Design Reconfigurable Algorithm Accelerator IP Block" by Tapio Ristimäki from Tampere University Of Technology / Institute of Digital and Computer Systems (Finland)

• "FPGA Coprocessors: Hardware IP for Software Engineers" by Robert Cottrel from Altera (UK)

• "A Fast SystemC Simulation Methodology for Multi-level IP/SoC Design" by Samy Meftali from LIFL (France)

• "IP-Based SOC Design in a in-house C-based design methodology" by Marcello Lajolo from NEC (USA)

• "An IP Based Design Flow with ASIPs for the Design and Implementation of Digital Filters" by Sven Simon from Hochschule Bremen (Germany)

• "Low-power Motion Estimation IP for MPEG-4" by Hongkyu Choi from Yonsei Univ. EE. (Republic of Korea)

• "Concepts and implementation of the Philips Network-on-Chip " by John Dielissen from Philips

• "SoC Integration of Programmable Cores" by A. Wieferink & T. Kogel from RWTH Aachen (Germany) & A. Hoffmann, O. Zerres & A. Nohl from CoWare Inc. (USA)

• "Transactional level as the new design and verification abstraction above RTL" by Bart Vanthournout from CoWare (Belgium)

• "IP Based System Design for Aerospace and Military - The Time is now" by P. Southard from PDS Consulting, LLC (USA) & T. Ivey from MTI (USA)

• "System for Active Design Knowledge Preservation and Reuse" by Chia-Huei Lee from Springsoft / Novas (Taiwan)

• "Sophocles: Cyber-Enterprise for System-On-Chip Distributed Simulation -- Model Unification"  by Pierre Boulet from LIFL (France)

• "Muti Chip, Multi Environment Simulation. Bringing Software closer to Hardware and saving $$" by Swaminathan Venkatesan from Wipro Technologies (India)

• "Dead Horse or Sleeping Beauty – Will Embedded FPGAs Have a Role in Future SoC-Designs?" by Thomas Niedermeier from Infineon Technologies (Germany)

• "Benefits of Reconfigurable IP in the Back-end SoC Development Process" by K. Lamb and T. Stansfield from Elixent Ltd (UK)

• "New architecture for Configurable blocks using Differential ANN" by Manjunath R & Gurumurthy from UVCE (India)

• "Recent Trends in Multi-Million-Gate Multimedia SOC Designs" by Santanu Dutta, IC Design manager at Philips Semiconductors (U.S.A)

• "Design platform for IP based SOC design" by Ted Vucurevich , CTO of Cadence (USA)

• "The IP Provider Game: Size and Diversity Do Matter" by Raul Camposano, CTO of Synopsys (USA)

• "Dataquest IP business analysis" by Jim Tully from Gartner / Dataquest (UK)