SOC VERIFICATION" SESSION
"IMPACT OF NANOMETER TECHNOLOGY"
"Selecting the Right Cell Library IP for Nanometer Technology"
Colwell & Gene Sluss from Virage Logic (USA)
"Maximize Design Flexibility with Fast Turnaround Time while
Design Costs with Metal Programmable Libraries"
by D. Sherlekar, O.
Siguenza & H. Yang from Virage Logic (USA)
"‘A la Carte’ SoCs require innovative IO management"
by David Murray
from Duolog Technologies (Ireland)
"ARCHITECTURAL DESIGN" SESSION
"IP BASED SOC DESIGN METHODOLOGY" OPEN
"Chip level IP for Low power Single chip Wireless Transceivers"
Faulkner from Jennic (UK) "BEST IP PRIZE" SESSION
"Scalable IP Core of Vector Stream Cipher"
by K. Umeno from
Communications Research Laboratory and Chaos Ware Inc. (Japan)
"REUSE PRACTICE" SESSION
"Lessons learnt in IP Reuse"
C.Gendarme, F.Kleitz &
I.Hrynchyshyn from Alcatel (France, Belgium), L.Ghanmi, M.Hamdoun &
B.Missaoui from Design and Reuse (France), K.Benseffaj, A.Hanczakowski
& M.Vandendriessche from STMicroelectronics (France)
"ASIC PLATFORM" SESSION
"An ASIC Platform Manager"
G.Saucier, K.Skiba, Ph.Rols &
Ph.Coeurdevey from Design And Reuse (France) & H.N. Nguyen from
METASymbiose S.A. (France)
"RECONFIGURABLE IP AND SOC" SESSION
"SYSTEMC FOR IP MODELLING" SESSION
"IP BASED SOC DESIGN" SESSION
"An IP Based Design Flow with ASIPs for the Design and
of Digital Filters"
by Sven Simon
from Hochschule Bremen (Germany)
"Low-power Motion Estimation IP for MPEG-4"
by Hongkyu Choi from Yonsei
Univ. EE. (Republic of Korea)
"SYSTEMC AND IP MODELLING" OPEN FORUM
"SoC Integration of Programmable Cores"
by A. Wieferink & T. Kogel
from RWTH Aachen (Germany) & A. Hoffmann, O. Zerres & A. Nohl
from CoWare Inc. (USA)
"Transactional level as the new design and verification
by Bart Vanthournout from
"Reuse Practice, Simulation &
FPGA & Reconfigurable IP" OPEN FORUM
"System for Active Design Knowledge Preservation and Reuse"
Chia-Huei Lee from Springsoft / Novas (Taiwan)
"Sophocles: Cyber-Enterprise for System-On-Chip Distributed
-- Model Unification"
Pierre Boulet from LIFL (France)
"Dead Horse or Sleeping Beauty – Will Embedded FPGAs Have a Role
Niedermeier from Infineon Technologies
"Recent Trends in Multi-Million-Gate Multimedia SOC Designs"
Santanu Dutta, IC Design manager at Philips Semiconductors (U.S.A)
"Design platform for IP based SOC design"
by Ted Vucurevich , CTO
of Cadence (USA)
"The IP Provider Game: Size and Diversity Do Matter"
Camposano, CTO of Synopsys (USA)
"Dataquest IP business analysis"
by Jim Tully from Gartner /