"IP BUSINESS MODEL" SESSION

• " One Approach to IP Cores: Ten Years and Going Strong" by Hal Barbour from CAST, Inc. (USA)

• " IP's Role in Developing the New Consumer Experience" by Cesar Martin-Perez from MIPS Technologies

"BEST IP PRIZE" SESSION

• " Development of an Arithmetic Operation System of a Variable Digit Number Type" by Hisashi Ito from CASIO COMPUTER CO., LTD. (Japan)

• " VUPU : Configurable Processor for C Level Design" by Yoshihide Sugiura from Pacific Design Inc. (Japan)

• " A 400µW MPEG-4 Motion Estimation Processor Core for Mobile Video Application" by Junichi Miyakoshi, Yuki Kuroda, Masayuki Miyama & Hideo Hashimoto from Kanazawa University (Japan) & Masahiko Yoshimoto from Kobe University (Japan)

• " PowerVR MBX - Creating an IP standard for advanced mobile multimedia" by Phil Atkin from Imagination Technologies (UK)

• "A Real-Time Video Smoothing IP Implementation using an FPGA-based Environment" by Ridha DJEMAL from LEM (Tunisia), Didier DEMIGNY from ETIS (France) & Rached TOURKI from LEM (Tunisia)

• " High-Speed Serial fully digital interface between WLAN RF and BB chips" by Michel Eftimakis & Mana Coste from NewLogic (USA)

• " Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture" by Yusuke Oike, Makoto Ikeda & Kunihiro Asada from University of Tokyo (Japan)

• " AICP: Aura Intelligent Co-processor for Binary Neural Networks" by Michael Freeman, Michael Weeks & Jim Austin from University of York (UK)

"IP SOC VERIFICATION" SESSION

• " Design of SystemVerilog Assertion IP" by Eduard Cerny from Synopsys, Inc. (USA), Janick Bergeron from Synopsys, Inc. (Canada) & Manoj Kumar Thottasseri from Synopsys, Inc. (India)

• " The Seven Steps of Formal IP Specification" by Harry Foster from Jasper Design Automation (USA)

• " Transaction-Level Modelling and Debug of SoCs" by Bassam Tabbara from Novas Software (USA) & Kamal Hashmi from SpiraTech (UK)

• " Hierarchical Assertion-based Verification" by H.N. Nguyen from Bull S.A. - METASymbiose S.A.S (France)

• " A Verification Environment Creation Infrastructure for Bus-based Systems and Modules" by Jorge Carrillo & Paulo Dutra from Xilinx (USA)

"DESIGN PLATFORM" SESSION

• " The Platform Based SOC Design that Utilizes Structured ASIC Technology" by Yu-Wen Tsai & Shun-Fu Chuang from Faraday Technology Corp. (Taiwan)

• " Philips Semiconductors Next Generation Architectural IP ReUse Developments for SoC Integration" by Geoff Mole from Philips Semiconductors (UK)

• " A Comprehensive Approach for Verification of OCP-based SOCs" by Riccardo Mariani & Natale Barsotti from YogiTech SpA (Italy)

• " SoC IP Qualifcation & Emulation Enviroment" by Mois Navon from Mobileye (Israel)

• " SOPC Builder, a Novel Design Methodology for IP Integration" by Stefano Zammattio from Altera Corporation (USA)

"REUSE PRACTICE" SESSION

• " A Web-Based Environment for the Evaluation and Generation of Complex IP Cores" by Angel Fernández Herrero, Miguel Angel Sánchez Marcos & Marisa López Vallejo from Universidad Politécnica de Madrid (Spain)

• " Challenges in developing a reusable IP core - USB OTG IP case study" by Haridas Vilakathra from Philips (India)

• " Reducing Time To Market for System On Chip Using Innovative IP Development and Integration Flows" by Sreekanth K.M (India), Lionel Dahyot (France), Rakesh Patnaik (USA) & Vinod Kumar (India) from Texas Instruments

"ASIC DESIGN PLATFORM" SESSION

• " NetComposer-II: High-Performance Structured ASIC Programmable NPU Platform for Layer 4-7 Applications" by C.J. Liang from Faraday Technology Corp. (Taiwan, R.O.C.)

• " A PowerPC SOC IO Processor for RAID applications" by Gerard Boudon, Thibaud Besson, Veronique Guerre, Pierre Debord & Jacques Rota-Biesdorf from IBM (France)

• " STBus Asynchronous Decoupler: an answer to the IP integration issues in future technologies" by Alberto Scandurra & Salvatore Pisasale from STMicroelectronics (Italy) & Daniele Mangano from University of Messina (Italy)

• " IP Processor Core Platform Selection According to SoC Architecture: a case study" by Yassine Aoudni & Nader Ben Amor from GMS/LESTER (Tunisia), Guy Gogniat & Jean-Luc Philippe from LESTER (France) & Mohamed Abid from GMS (Tunisia)

"VERIFICATION" SESSION

• " Reusable Verification Environment for Core based Designs" by Teng-Peow Ng, Anjali Vishwanath, Rizal Prasetyokusuma & Ranga Kadambi from Infineon Technologies (AP) Pte Ltd (Singapore)

• " Debugging SOC Designs with Transactions" by Rich Edelman, Bill Cox & Mark Glasser from Mentor Graphics (USA)

• " Is IP Quality Achievable, Measurable and Enforceable through the Design Chain?" by Saverio Fazzari from Cadence Design Systems (USA) & Dan Moritz from Virage Logic (USA)

• " System Verification Methodology (sVM) applied to Transaction Level SystemC models" by Giles Hall from Verisity

"REUSE PRACTICE" OPEN FORUM

• " The Challenge of Keeping IP Usable" by Phil Rose from Cadence Design Systems (UK)

• " DesignJet: A Project Management Platform for Collaborative IC Design" by Charles Trappey from National Chiao Tung University (Taiwan), Amy J.C. Trappey, Jiang Liang Hou & Ker Jeng Chang from National Tsing Hua University (Taiwan) & Shiu Yuan Shih from Avectec.com, Inc (Taiwan)

• " Solving The IP Selection Problem: Are Quality Metrics Enough?" by Saverio Fazzari & Jean-Michel Fernandez from Cadence Design Systems (USA)

• " IP Exchange Procedure: a light formalism to improve communication between IP suppliers and integrators" by Rosamaria Balestri from STMicroelectronics (italy)

"DESIGN METHODOLOGY" SESSION

• " Physical Design for Reuse: Strategies and Implementation" by Ralph Escherich & Lane Albanese from ReShape Inc. (USA)

• " Vertical Solution for PCI Express" by Ken Reid from Cadence Design Systems (UK)

• " The right IP for your SerDes needs" by Leo Wong from Rambus (USA)

• " A Design of System on a Chip for Voice over Wireless LAN" by Hun-sik Kang, In-ki Hwang, Chan-won Park, Gi-jong Koo & Jae-ho Lee from ETRI (Korea)

• " Low power microcontroller design techniques for mixed-signal applications" by Ron Landry from AMI Semiconductor (USA)

• " Simultaneous Exploration of Power, Physical design, and Architectural Performance Dimensions of SoC Design Space using SEAS" by Nagashyamala (Nagu) R. Dhanwada from IBM Electronic Design Automation (USA)

• " Die Level Process Monitoring for Mixed Signal Designs" by Bert Vermiere from Ridgetop (USA), Eckardt Bihler from Forturex (Germany) & Doug Goodman from Ridgetop (USA)

"INDUSTRIAL IP DESIGN PRACTICE" SESSION

• " Unleashing the Power of Embedded DRAM" by Peter Gillingham from MOSAID Technologies (Canada)

• " Automated Transistor-Level Optimization in Standard-Cell Based Digital Design" by Rob Roy & Debashis Bhattacharya from Zenasis Technologies (USA)

• "Rapid Protocol Stack development Framework" by Vinaychandra A V S & Girish Dandin from Wipro technologies (India)

"MULTI-PROCESSOR AND MULTI-THREAD SOC" SESSION

• " Understanding and Extending SystemC User Thread Package to IA-64 Platform." by Joël Vennin from Prosilog, Samy Meftali & Jean-Luc Dekeyser from LIFL - Lille 1 University (France)

• " Interface Synthesis in Multiprocessing Systems-On-Chips" by Francesco Regazzoni from University of Lugano (Switzerland) & Marcello Lajolo from NEC USA (USA)

"VERIFICATION" OPEN FORUM

• " Efficient Verification of CAN based System" by Rajesh Thyagarajan & Pitchumani Guruswamy from Wipro Technologies (India)

• " Addressing IP Reuse with Formal Verification and Assertion Based Verification" by Andrea Fedeli, Matteo Moriotti & Franco Toto from STMicroelectronics (Italy)

• " System Verification Methodology sVM: A Reuse Verification Methodology from Module-level to System-level" by Imed Moussa, Hannes Froehlich & Patrick Oury from verisity Design (France)

"DESIGN METHODOLOGIES" OPEN FORUM

• " Performances Estimation Metamodel for MDA Based SoC Design" by Mickael Samyn & Samy Meftali from LIFL, Smail Niar from LAMIH-ROI & Jean-Luc Dekeyser from LIFL (France)

• " A SystemC based Virtual Prototyping Methodology for Embedded Systems " by Paul Lister, Mike Bassett, Phil Watten, Vincezo Trignano & Ben Jackson from University of Sussex (UK)

• " Unparalleled Re-Use Driven by Rule-Based Design " by Geoff Steckel from Bluespec Inc.