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IP07 Conference Presentations

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KEYNOTE TALK / PANEL

• "Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects " by Ron Collett, CEO of Numetrics Management Systems, Inc. (Audio + Slides)
  
  
• "Standards-Based IP - The Last And The Next Decade " by Joachim Kunkel, VP/GM Solutions Group, Synopsys (Audio + Slides)
  
  
• "Next Chapter in IP: Enabling Innovation " by Gagan Gupta, Senior Director of Product Marketing, ARC International (Audio + Slides)
  
  
• "A Decade in Library IP and Mixed Analog IPs " by Bob Tait, Marketing Director of Consumer Silicon, Silicon & Software Systems (Audio + Slides)
  
  

IP DESIGN

• "FPGA based Complex System Designs: Methodology and Techniques" by Kodavalla Vijay Kumar from Wipro Technologies (Full Paper)
  
  
• "A FPGA-based solution for enforcing dependability and timeliness in CAN" by José Rufino from FCUL, Ricardo Pinto & Carlos Almeida from IST-UTL (Full Paper)
  
  
• "Performance Enhancements in System Packet Interface (SPI) 4.2 IP Core" by Kaushal Buch, Tarang Popat & Rahul Jain from eInfochips Ltd (Full Paper)
  
  
• "H.264/AVC HDTV Motion Compensation Soft IP" by Bruno Zatt, Arnaldo Azevedo, Luciano Agostini, Altamiro Susin & Sergio Bampi from UFRGS (Full Paper)
  
  
• "AMASS Core: Associative Memory Array for Semantic Search" by Pal Rujan from LCI GmbH, Francois Vuillod & Benedikt Gomm from UniUlm & Marius Monton & David Castells from UAB (Full Paper)
  
  
• "IP Core of On-line ICA Algorithm" by Song-Ju Kim from NiCT & Hideaki Terai & Ken Umeno from NiCT, ChaosWare Inc. (Full Paper)
  
  
• "Dual Mode SMIA/MIPI Receiver Supporting 2Gbps" by Yoav Lavi from VLSI Plus (Full Paper)
  
  
• "A 0.79-mm^2 29-mW Real-Time Face Detection IP Core" by Yuichi Hori & Tadahiro Kuroda from Keio University (Full Paper)
  
  
• "A fully generic FEC generator for ASIC/FPGA" by Amir H. Farahani, Shahin Haghi Tabrizi, Mohammad Khalilzadeh & Jeyran Hezaveh
  

POWER OPTIMIZATION

• "Predictable, Automated Verification of Protocol Compliance : Methodology Guidelines and Best Practices for Achieving Compliance Closure" by Dimitry Pavlovski, Moshik Rubin & Liron Stoler from Cadence Design Systems, Inc.
  
  
• "Mixed Signal Drivers for Ultra Low Power and Very High Power Applications" by Offer Schwartsglass, Ph.D. from Avnet ASIC Israel (Full Paper)
  
  
• "Accurate System Level Power Estimation through Fast Gate-Level Power Characterization" by Philippe Soulard & Sue Xu from NXP Semiconductors
  
  
• "Low Power Transport Demultiplexer for ATSC and DVB Broadcast Formats" by jalaj jain & Pravin Desale from LSI Logic (Full Paper)
  
  
• "Pushing the Frontier in Managing Power in Embedded ASIC or SoC Design with PCI Express" by CC Hung, Mentor Graphics & Kishore Mishra, ASIC Architect, Inc (Full Paper)
  
  

HIGH LEVEL MODELING

• "Adapter Based Distributed Simulation of Multiprocessor SoCs Using SystemC" by Aravinda Thimmapuram from NXP Semiconductors
  
  
• "Accelerating High-Level SysML and SystemC SoC Designs " by Waseem Raslan from Mentor Graphic Egypt & Ahmed Sameh from The American University in Cairo (Full Paper)
  
  
• "SystemC Mixed-HDL IP Reuse Methodology" by Rudra Mukherjee, Gaurav-Kumar Verma & Arnab Saha from Mentor Graphics
  
  
• "Modelling Embedded Systems at Functional Untimed Application Level" by Sandro Penolazzi, Ahmed Hemani & Mohammad Badawi from KTH
  
  
• "Rapid Creation of Application Models from Bandwidth Aware Core Graphs" by Joao Otero from NEC Laboratories America, Francesco Regazzoni from ALaRI & Marcello Lajolo from NEC Laboratories America
  

IP BUSINESS MODEL

• "IP Monetization: Your technology or your patents" by Mike McLean from Semiconductor Insights
  
  
• "The Gaisler Research Open-Source Business Model" by Per Danielsson from Gaisler Research
  
  
• "ESA IP Cores Service" by Kostas Marinis & Agustin Fernandez-Leon from ESTEC/ESA
  

IP MANAGEMENT, DELIVERY AND EXCHANGE

• "Collaborative engineering approach towards IP-based SoC design" by Adam Pawlak, Piotr Penkala & Pawel Fras from Silesian University of Technology, Havard Jorgensen from AKM AS & Wojciech Sakowski from Evatronix SA
  
  
• "IP Tagging and Tracing in IP centric Design, Project and Product management" by Gabrièle Saucier & Philippe Ozil from Design And Reuse
  
  
• "A Semi-automatic IP Distribution Tool" by Millena Gomes, Cristiano Araujo, Felype Santiago & Edna Barros from UFPE
  
  
• "IPGenius, an on-line configurable IP Generator" by Iakovos Stamoulis, Polytimi Kolokytha, Theodore Roudas & George Sidiropoulos from Think Silicon Ltd (Full Paper)
  

IP INTEGRATION AND STANDARDS

• "A Chip IP Integrator for System Level Design" by Mikhail Baklashov from ARM, Inc. (Full Paper)
  
  
• "Generic Driver Model using hardware abstraction and standard APIs" by Amar Amar, Shirish Joshi & Don Wallwork from Cisco Systems Inc
  
  
• "SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker" by Jan Langer, Vasco Jerinic from Chemnitz University of Technology & Ulrich Heinkel from Chemnitz University of Technology, Frank Dresig from AMD Saxony LLC and Co. KG & Jan Langer (Full Paper)
  
  

IP ENCRYPTION

• "DesignTag: A Thermally Sensed Security Tag to Protect Chip Designs" by Tom Kean from Algotronix Ltd, David McLaren & Carol Marsh from Algotronix Ltd. and ISLI
  
  
• "Hardware Security Requirements for Embedded Encryption Key Storage" by Craig Rawlings from Kilopass Technology Inc. & Brian Neill from Certicom
  
  

VERIFICATION

• "A Comparison of Assertion Based Formal Verification with Coverage driven Constrained Random Simulation, Experience on a Legacy IP" by Jentil Jose & sachin Abdul Basheer from Wipro Technologies
  
  
• "Re-Use of Unit level verification environment for verification of memory controller" by Aniruddha Baljekar from NXP Semiconductors
  
  
• "Case Study: Annotating OVL 2.0 with SVA Assertions" by Jiang Long, Andrew Seawright, Bipul Talukdar, Vibarajan Viswanathan & Kenneth Larsen from Mentor Graphics
  
  
• "Virtual Prototyping Environment for Multi-core SoC Hardware and Software Development" by Syed Abrar from NXP
  
  
• "Creating Interoperable and Reusable Verification IP in SystemVerilog with the Open Verification Methodology (OVM)" by John Rose & Dave Tokic from Cadence Design Systems, Inc. & Dennis Brophy from Mentor Graphics Corporation
  
  
• "Advanced techniques for IP design and verification" by Rangarajan Sundaravaradan & Vishwanath Balasubramanian from NXP Semiconductors
  
  
• "SystemC: Key modeling concepts besides TLM to boost your simulation performance" by Martin Schnieringer from VaST Systems Technology
  
  
• "Your Verification Methodology Ran Out of Steam and Your Project is Failing : How to Quickly Ramp Your Team and Apply the Latest Techniques to Tape Out Successfully" by Nick Heaton & Hamish Hendry from Cadence Design Systems, Inc.
  
  
• "Staged Scenario Generation For SoC Verification" by Sidhesh Patel & Prakash Bodhak, LSI Corporation (Full Paper)
  
  

CONFIGURABLE PLATFORM

• "A configurable FPGA-based multi-channel high-definition Video Processing Platform" by Kambiz Khalilian from Omaha Microsystems & Bernd Merkl from Visual Communication Systems
  
  
• "A Configurable HW/SW Platform for Video Application" by ahmed ben atitallah from ENIS, Patrice Kadionik from IMS, Nouri Masmoudi from ENIS & Hervé Levi from IMS
  
  
• "Designing FPGA Based Reliable Systems Using VirtexTM-5 System Monitor" by Sanjay Kulkarni from Xilinx
  
  
• "Configurable SoC Platform for Bluetooth Applications" by Santosh Shivadatta & Srinivasan Nachiappan from MindTree Consulting Ltd
  

NoC AND INTERCONNECT

• "Placement of different type nodes in a Network-on-chip graph" by Elena Suvorova & Yuriy Sheynin from Saint-Petersburg University of Aerospace Instrumentation
  
  
• "An HDTV SoC based on a mixed circuit-switched / NoC interconnect architecture (STBus/VSTNoC)" by Ignazio Urzi, Claire Bonnet, Philippe D'Audigier & Olivier Sauvage from ST Microlectronics
  
  
• "Performance verification methods developed for an HDTV Soc integrating a mixed circuit-switched / NoC interconnect (STBus/VSTNoC)" by Claire BONNET, Ignazio URZI, Philippe D'AUDIGIER & Olivier SAUVAGE from STMicroelectronics
  

ARCHITECTURAL SYNTHESIS

• "USB Host IP-Core Hardware And Software Concurrent Development" by Adelmario Douglas from UFPE (Full Paper)
  
  

TEST BENCH AND SIMULATION

• "eTBc: A Semi-Automatic Testbench Generation Tool" by Isaac Maia & Karina R. G. da Silva from LINCS/CETENE, Leandro Max, Romulo Camara & Elmar U. K. Melcher from Federal University from Campina Grande
  
  
• "Validation Approaches for a Product Family" by Leela Bhaskarabhotla, Mee Hing He & Anjali Vishwanath from Infineon Technologies Asia Pacific Pte Ltd,
  
  
• "Upfront Analysis of Low Power Specification, Assertions and Testbench to Enable Reuse" by Kanwar Singh from Cadence Design Systems
  
  
• "Automated Test-Bench for Mobile Applications" by Ashwin Kumar T.C. from NXP Semiconductors India Pvt. Ltd. (Full Paper)
  
  

SoC DESIGN

• "Automation in IP based SoC development: Case study of a media processor subsystem" by Haridas Vilakathara from NXP semiconductor
  
  
• "Improving design turn around time on a complex SoC by leveraging a reusable low power specification" by Herve Menager, Michel Korenhof & Michiel Huiskes from NXP Semiconductors (Full Paper)
  
  
• "H.264 baseline decoder with ADI Blackfin DSP and hardware accelerators" by Anand V Kulkarni from Wipro Technologies & Shankar Malladi from Analog Devices Inc. (Full Paper)
  
  
• "Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)" by Mohit Arora, Freescale Semiconductor (Full Paper)
  
  
• "Secure Your Security Key in On-Chip SRAM: Techniques to avoid Data Remanance Attacks" by Mohit Arora, Freescale Semiconductor (Full Paper)
  
  

ANALOG MIXED SIGNAL

• "Building High-Quality, Mixed-Signal IP in 65-nm and Beyond " by Dino Toffolon & Navraj Nandra from Synopsys (Full Paper)
  
  
• "Mixed-Signal Verification for USB 2.0 Physical Layer IP" by Hany Bakeer, Omar Shaheen & Haitham Eissa from Mentor Graphics
  
  
• "UWB Time-interleaved ADC exploiting SAR" by Silvia Dondi, Marco Bigi, Andrea Boni & Matteo Tonelli from Silis s.r.l. (Full Paper)
  
  

BACK END DESIGN

• "Integration of Design-for-Analysis in IC Layout Design in meeting the Challenges of Shrinking Technology" by Khim-Hou Lee from Infineon Technologies
  
  
• "IP Gate Count Estimation Methodology during Micro-Architecture Phase" by Kodavalla Vijay Kumar from Wipro Technologies
  

IP DESIGN METHODOLOGIES

• "Software - the X factor" by Chris Turner from Cambridge Consultants (Full Paper)
  
  
• "Timing annotation of UnTimed Functional models for architecture use-case" by Rajiv Gupta from HCL Technologies
  
  
• "Real-World Reuse: RTL Recycling" by Tom Dewey & Gordon Walker from Mentor Graphics Corp.
  
  
• "Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Validation" by Pankaj Singh from Texas Instruments India (P) Ltd
  
  

IP BEST PRACTICES

• "The PCIe IP Market consolidating. Is it necessarely the Commoditization of the PCIe IP?" by Eric ESTEVE
  
  
• "The good? The bad? The ugly? IP Perspectives from Vendor to SOC Designer" by Navraj Nandra from Synopsys, Inc, David Chiapinni from Matrox & Massimo Vanzi from Accent (Full Paper)
  
  
• "Designing Around an Encrypted Netlist: Is The Pain Worth the Gain?" by Scott Barrick from Mentor Graphics
  
  
• "A Different Path to IP Success: A Decade-Plus Delivering Cores the CAST Way" by Hal Barbour from CAST, Inc.
  

TEST AND SIMULATION

• "Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Bring-up" by Pankaj Singh from Texas Instruments India (P) Ltd
  
  
• "Development and use of an Instruction Set Simulator of 68000-compatible processor core" by Filip Rak from Evatronix SA & Wojciech Sakowski from Silesian University of Technology
  
  
• "Preservation of Circuit Structure and Timing during Fault Emulation in FPGA" by Leos Kafka & Martin Danek from UTIA AV CR & Ondrej Novak from Czech Technical University in Prague
  

SYSTOLIC AND 2D ARRAY

• "Systolic FIR Filter IP Based FPGA" by Abdelhamid GOUGAM & Djamel Benazzouz from University of Boumerdes
  
  
• "An Efficient Software-Hardware Partitioning for Transport Demultiplexer" by jalaj jain & Pravin Desale from LSI Logic
  
  
• "An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs" by Imran-Rafiq Quadri, Samy Meftali & Jean-Luc Dekeyser from LIFL, USTL, INRIA FUTURS
  
  
• "VLSI Based On Two-Dimensional Reconfigurable Array Of Processor Elements And Theirs Implementation Of Numerical Algorithms In Real-Time Systems" by Nick Lookin from Institute of Engineering Science, Vadim Bersenev from Urals Division of RAS & Michael Trapeznikoff from SPAA
  

EXHIBITOR TRACK

• "Dassault Systèmes ENOVIA" by Felix Beniamine
  
  
• "Analog and Mixed-Signal design solutions for SoC makers" by Thierry Delmot from nSilition
  
  
• "Satin IP Technologies, Enabler of Semiconductor Design-for-Reuse" by Michel Tabusse
  
  
• "A solution for Noise impact in Analog Mixed Signal SoC" by Brieuc Turluche (CWS)
  
  
• "LEON3 and the GRLIB IP-library" by Per Danielsson (Gaisler)
  
  
• "The AMASS Project: a general in-memory search platform for database, text, semantic web, and multimedia management applications" by Dr. Pal Rujan from LCI GmbH
  
  
• "Ultra-Low Power? Think Multi-ASIP SoC!" by Gert Goossens from Target Compiler Technologies
  
  
• "EVE" by Luc Burgun
  
  
• "Accelerating Product Development with IP Subsystems" by Rick Tomihiro from Mentor Graphics
  
  
• "What's missing? An efficient intranet IP Reuse infrastructure" by Gabriele Saucier from Design And Reuse
  
  
• "ASIC Prototyping with FPGAs" by Mike Dini from The Dini Group
  
  
• "A Formal Verification Process to Ensure Error-free IP" by Michael Siegel from OneSpin Solutions
  
  
• "Breaking the 10G Barrier" by Tony Pialis from Snowbush/Gennum
  
  
• "Ansoft, High Performance EDA Software" by Rémy Fernandes from Ansoft