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IP08 Conference Presentations

Missed IP08 Conference ? Or just want to review what you have heard in a session ? See IP 08 Presentations from IP Industry Leaders online.

Keynote Talks

• "IP Reuse leading the way of Enterprise level IP management" by David Yoon, Sr. Manager of IP Management, Cisco systems
  
  
• "IP management platforms: A success story" by Gabriele Saucier, CEO, Design And Reuse (Audio + Slides)
  
  
• "Feeding the Beasts: Optimized Shared Memory Solutions for MPSoCs" by Drew Wingard, CTO, Sonics (Audio + Slides)
  
  
• "Behavioral Indexing: A Breakthrough in Design Reuse and IP Modification" by Kathryn Kranen, President and CEO, Jasper Design Automation (Coming soon ....)

Standard & Integration

• "The Value of High Quality IP-XACT XML" by Marc van Hintum1 Hintum from NXP Semiconductors & Paul Williams from Mentor Graphics (Full Paper)
  
  
• "Assisted creation and refinement of transactional level specifications based on IP-XACT" by Nicolas Laug, Guy Bois & Marc-André Cantin from École Polytechnique de Montréal
  
  
• "Refactoring to Prepare RTL for Reuse" by Steve Haynal from Intel Corporation (Full Paper)

Configurable Systems

• "Tailored SoC building using reconfigurable IP blocks" by Lodewijk Smit, Gerard Rauwerda, Jochem Rutgers, Maciej Portalski & Reinier Kuipers from Recore Systems (Full Paper)
  
  
• "CUSTOMIZABLE SoC SPEAr® FROM STMicroelectronics SOLVING TIME TO MARKET ISSUES" by Matteo Mazzola, Bruno Cristofoli, Henry Le Henaff & Alain Pasteur from ST
  
  
• "Enabling Secure Integration of Multiple IP Cores in the Same FPGA" by Bassel Soudan from University of Sharjah, Wael Adi from Technical University of Braunschweig, Abdulrahman Hanoun from Technical University of Hamburg

IP Design

• "Practical Design and Implementation of a Configurable DDR2 PHY" by Lior Amarilio from ChipX (Full Paper)
  
  
• "A generalized waveform synthesis mechanism for software radio" by Maurizio Colizza & Fabio Graziosi from Westaquila, Claudia Rinaldi from University of L'Aquila (Full Paper)
  
  
• "DDR SDRAM Controller IP Designed for Reuse" by Alexsandro Bonatto, André Soares & Altamiro Susin from UFRGS (Full Paper)
  
  
• "Stochastic Computation applied to the design of Error Correcting Decoders" by Gordon Harling from WideSail Technologies, Warren Gross & Shie Mannor from McGill University
  
  
• "A multi-purpose Digital Controlled Potentiometer IP-Core for nano-scale Integration " by Reimund Wittmann, Ralf Kakerow & Harald Bothe from IP Gen Rechte GmbH, Werner Schardein from University of Applied Sciences and Arts, Dortmund (Full Paper)
  
  
• "uBIP: A Simplified Microcontroller Architecture for Education in Embedded Systems Design " by Maicon PEREIRA & Cesar ZEFERINO from UNIVALI
  
  
• "A 1-10Gbps SerDes IP in 65nm CMOS Technology" by Afshin Rezayee, Angus McLaren, Saman Sadr, Robert Wang & Mehrdad Ramezani from SnowbushIP
  
  
• "Debug and testability features for multi-protocol 10G SerDes" by Claude Gauthier, Shaishav Desai & Sanjay Dabral from Prism Circuits
  
  
• "H.264 Baseline Encoder With ADI Blackfin DSP and Hardware Accelerators" by Anand V Kulkarni, Wipro Technologies and Shankar Malladi, Analog Devices Inc. (Full Paper)

SoC Design and Reuse

• "Embedded Software Architecture Specification Developments in Support of SoC Design and Re-use" by Robert Deaves, Andrew Jones & Stuart Ryan from STMicroelectronics
  
  
• "SoC IP Interfaces and Infrastructure: A Hybrid Approach" by Cary Robins & Shannon Hill from ChipWrights
  
  
• "A Re-Usable Level 2 cache Architecture" by Andrew Jones, Mark Hill, Mark Beaumont, James Pascoe & Stuart Ryan from STMicroelectronics
  
  
• "IP-based toolbox for digital signal processing reuse: Application to Real-time Spike sorting" by Timothée Levi, Jean-François Bêche, Stéphane Bonnet & Régis Guillemaud from CEA-LETI, DTBS/STD/LE2S
  
  
• "A Cost-Optimized Set-Top Box Architecture" by Stuart Ryan from STMicroelectronics, Andrew Jones from STMicroelectronics, Robert Deaves from STMicroelectronics
  
  
• "Migrating from SPI 4.2 to SPI 5 IP Core – Architectural Changes and Re-usability" by Kaushal Buch from eInfochips Ltd.

High Level Modeling

• "An UML-driven Interface Generation Approach for SoC Design with Synthesizable SystemC Code Generation" by André Aziz, Francielle Santos, Daniele Santos, Millena Gomes & Edna Barros from Informatics Center. Federal University of Pernambuco
  
  
• "Launchers Avionic Chains modelling based on SystemC for early Hardware-Software breakdown and Interfaces definition" by Arnaud Stransky & Laurent Chevalier from Astrium
  
  
• "Advances in SoC and Processor Modeling Methodologies" by Syed Saif Abrar from NXP
  
  
• "How high-level synthesis can raise the efficiency of design reuse" by Thomas Bollaert from Mentor Graphics Corporation
  
  
• "UML-based Design of a JPEG-LS IP via Axilica FalconML" by Scott Moyers, Robert Thomson, Vassilios Chouliaras & David Mulvaney from Axilica
  
  
• "SystemVerilog-VHDL-SystemC Verification IP Reuse Methodology" by Gaurav Kumar-Verma & Rudra Mukherjee from Mentor Graphics

Business Model

• "from IP re-use to Open Innovation: a new industry trend" by Patrick Blouet from STMicroelectronics
  
  
• "Break-up of the Fabless Semiconductor Model – Has the time come?" by Paul Slaby from Kaben Wireless Silicon (Audio + Slides)
  
  
• "In 2010, PCIe, SATA and USB IP Market will represent $200M" by Eric Esteve from Snowbush (Consultant)

IP Quality

• "Embedded Software IP Verification" by Markus Winterholer from Cadence Design Systems
  
  
• "Requirements for intellectual properties in safety critical airborne electronic hardware" by Pascal Pampagnin from airbus
  
  
• "ipPROCESS: A Usage of an IP-core Development Process to Achieve Time-to-Market and Quality Assurance in a Multi Project Environment" by Francielle Santos, André Aziz, Daniele Santos, Millena Gomes & Edna Barros from Federal University of Pernambuco
  
  
• "Semiconductor IP Quality – A User guide" by Gerardo Nahum & Omri Raisman from Rosetta IP

NoC & SoC

• "A Twenty-four Processors System on Chip FPGA Design" by Zhoukun Wang & Hammami Omar from ENSTA ParisTech

Prototyping

• "A Platform for Performance Validation of memory controllers" by Ramchandra Vibhute, Manikandan Panchapakesan & Haridas V from NXP semiconductors, Bangalore
  
  
• "Embedded software development using an interpretive instruction set simulator" by Wojciech Sakowski from Institute of Electronics, Silesian University of Technology & ?ukasz Mirek & Filip Rak from Evatronix
  
  
• "Fast Design Productivity for Embedded Multiprocessor Through Multi-FPGA Emulation The case of a 48-way Multiprocessor with NOC " by Xinyu LI & Omar HAMMAMI from ENSTA ParisTech
  
  
• "EDA tools and Design Methodology for multi-FPGA Designing/ Prototyping" by Barun Kumar De & Shridhar Laddha from SoftJin Technologies Pvt. Ltd.
  
  
• "Developing high simulation speed VLIW processor model for software development" by Mohit Paul & Syed Saif Abrar from NXP

Technology Impact

• "Analog IP Integration in SoC: Challenges and Solutions" by Pankaj Singh from Infineon Technologies
  
  
• "Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes" by Dan Hillman from Transmeta Corporation
  
  
• "Comprehensive tool for on-chip ESD protection design to achieve first-time-right success" by Bart Keppens, Ilse Backers, Wim Vanhouteghem & Pieter Donck from Sarnoff Europe

Verification

• "Automating Protocol Compliance Verification Using Metric Driven Verification" by Erez Kovshi, Tamar Meshulum, Levent Caglar & Pete Heller from Cadence Design Systems
  
  
• "Finding out the right verification methodology for SOC verification" by Rajiv Gupta from HCL TECHNOLOGIES LTD
  
  
• "Learning Not to Fear PCI Express Compliance Using a Predictable, Metrics Driven Methodology" by Mike Bartley & Jim Hutchinson from ClearSpeed Technology Plc & Dimitry Pavlovsky & Pete Heller from Cadence Design Systems
  
  
• "Transactions in an OVM SystemVerilog Verification Environment" by Rich Edelman from Mentor Graphics
  
  
• "Trace Based Approach for Unit Level Debug and Verification of C/C++ IP Models" by Amit Nene & Swaminathan Ramachandran from Texas Instruments (Full Paper)

Other

• "Field programmable signal processing arrays using 2d micro architecture" by Krrishna kumar kp from RASET