Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
Verification Framework for IO Accelerators using SV Models
By Ajay BS (Veriedge Technologies)
Biography
Ajay.B.S is currently working as Senior Verification Engineer at Veriedge Technologies Pvt. Ltd., a Bangalore based company with the responsibility of developing Design verification platform for IO Accelerators. Prior to joining Veriedge Technologies, Ajay was a Consultant Design Engineer for Cadence AMS Design Systems India Pvt. Ltd. He holds Master degree in Digital Electronics and Advanced Communication from Manipal University, Manipal in India.