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IP DAY: Tuesday December 1, 2009
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7:00 - 8:45
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Breakfast
and Registration
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AUDITORIUM |
| 8:45 - 9:00 |
Welcome
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9:00 - 9:45
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Keynote Talk: Keynote Talk: The 21st Century Business Model Adventure
 By Eric Schorn
Vice President of Marketing, Processor Division
ARM Ltd
The 21st Century Business Model Adventure
By Eric Schorn, Vice President of Marketing, Processor Division, ARM Ltd
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| 9:45 - 10:30 |
Keynote Talk: Keynote Talk: Strategies for Managing SoC IP Risks at Advanced Process Nodes
 By Yervant Zorian
Vice President & Chief Scientist
Virage Logic
Strategies for Managing SoC IP Risks at Advanced Process Nodes
By Yervant Zorian, Vice President & Chief Scientist, Virage Logic
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| 10:30 - 11:00
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Break
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AUDITORIUM |
KILIMANDJARO
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MONT
BLANC
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MAKALU
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| 11:00 - 12:30
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Panel: IP Reuse vs. IP Leverage: What's the difference, and what are the issues?Panel: IP Reuse vs. IP Leverage: What's the difference, and what are the issues?
Moderator:
 Kathryn Kranen
President and CEO
Jasper Design Automation
Panelists:
- Sanjay K. Srivastava, President, CEO , Denali
- Andrea Fortunato , European Director of Professional Services, Numetrics
- Olivier Haller, STMicroelectronics
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Invited Talk: Invited Talk: IP reuse doesn’t sell systems!
 By Richard Bramley
Head of Mobile Platform System Architecture
ST-Ericsson
IP reuse doesn’t sell systems!
By Richard Bramley, Head of Mobile Platform System Architecture, ST-Ericsson
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Seminar: Future in IP interconnects: optical, 3-D, wireless, what are the main challenges?Seminar: Future in IP interconnects: optical, 3-D, wireless, what are the main challenges?
Organizer:
 Fabien CLERMIDY & Daniel VELLOU
CEA/LETI
Speaker:
- Luca Benini, University of Bologna
- Haykel Ben Jamaa, EPFL
- Laurent Fulbert, CEA-LETI
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Workshop
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| 12:30 - 13:30
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Lunch
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| 13:30 - 15:00 |
Panel: The evolution of semiconductor business models: is the fabless dead or alive and kicking?Panel: The evolution of semiconductor business models: is the fabless dead or alive and kicking?
Moderator:
 C. Paul Slaby
Kaben Wireless Silicon Inc
President & CEO
Panelists:
- Stan Swirhun, Senior VP & GM, Optical Products Group, Zarlink Semiconductor
- Kalar Rajendiran, Senior Director, Marketing, eSilicon
- Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
- Jean-Philippe Gendre, Investment Director, Emertec
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Session: IP Business Model & StandardizationSession: IP Business Model & Standardization
Chairman: Pierre Bricaud (Synopsys)
-"Innovation led Business Models for IP’s in Product Engineering" by Madhu Parthasarathy (WIPRO Technologies)
-"Diffusion of USB 3.0 innovation: IP market forecast for 2009-2010" by Eric Esteve (IPnest)
-"Achieving Higher Productivity using IP Re-Use and Standardization" by Prasad Shenoy (NXP )
-"IP Re-engineering and Design Methodology" by Akash Apasangi (MindTree Ltd)
-"Arasan’s Portfolio of MIPI® IP - Fostering Innovation with Standardized Interconnect" by Somnath Viswanath (Arasan Chip Systems)
-"Creating a Virtual Platform using OCP kit" by Puneet Arora (CircuitSutra)
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Session: Analog DesignSession: Analog Design
Chairman: Kunihiko Tsuboi (STARC )
-"Analog IP Porting by Topology Conversion and Optimization" by Udo Sobe (ZMD AG) 
-"A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS" by Dino Toffolon (Synopsys)
-"A Methodology for Describing Analog/Mixed-Signal Blocks as IP" by João Vitor Pimentel (Universidade de Brasília)
-"Design Methodology Using Verilog Models" by Ignatius Bezzam (Arasan Chip Systems Inc.)
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Workshop
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| 15:00 - 15:30 |
Break |
| 15:30 - 17:00
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Panel: Total IP Solutions for Enabling Technology AdoptionPanel: Total IP Solutions for Enabling Technology Adoption
Moderator:
 Paul Dempsey
Editor-in-Chief
EDA Tech Forum Journal
Panelists:
- Ram Gopalan, Senior Director of Marketing, Arasan Chip Systems
- Arthur Marris, Staff Design Engineer , Cadence Design Systems Inc.
- Andre Picco, ST Ericsson
- Atul Bhatia, President & CEO, nSys Design Systems
- Ignatius Bezzam, Senior Director of Engineering , Arasan Chip Systems
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Session: DesignSession: Design
Chairman: Paolo Pezzati (Cadence)
-"A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration" by Pankaj Singh (Infineon Technologies)
-"Design of an image-processing device for cost-sensitive, high-volume applications using a novel dynamically-reconfigurable technology" by Colin Dente (Akya Limited)
-"Design and Implementation of a USB On-The-Go Controller IP Core" by Deepu Krishnan (Centre for Development of Advanced Computing)
-"RTOS Co-Processor Implementation in VHDL" by Carlos Ferreira (University of Aveiro)
-"Power Optimization for Image Super Scalar IP" by Akhilesh Mahajan (Samsung India Software Operation)
-"IP reuse in Processor based MCU Development" by Anand Mahalingam (KPIT)
-"Design of a 4-Channel 16-Bit Solid State Drive" by Jamshid Dastur (NED University of Engineering and Technology)
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Seminar: Enterprise platform for Internal and External IPs managementSeminar: Enterprise platform for Internal and External IPs management
Speaker:
- Gabriele Saucier, CEO, Design And Reuse
- Philippe Ozil, Design And Reuse
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European SystemC User's Group Meeting
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| 17:00 - 17:15
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Break |
| 17:15 - 18:45
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Panel: Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?Panel: Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?
Moderator:
 Phil Dworsky
Synopsys
Panelists:
- François Rémond, Director, CAD & Design Methodology, STMicroelectronics
- Philippe Di Crescenzo, Director of Engineering , Arteris
- Kathryn Kranen, President and CEO, Jasper Design Automation
- Michel Tabusse, Co-founder, president & CEO, Satin IP Technologies
- Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
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Session: PrototypingSession: Prototyping
Chairman: Helena Krupnova (STMicroelectronics)
-"Partial reconfiguration in FPGA rapid prototyping tools" by Raul Torrego (Ikerlan-IK4)
-"FPGA Designer GUI Tools Suite: A complete hardware and software infrastructure for creating customizable eFPGA IP blocks of Menta®" by Syed Zahid Ahmed (Menta)
-"Configurable Design and Verification Platform for SOC" by Swapnil S (MindTree Ltd)
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Session: Design MethodologySession: Design Methodology
Chairman: Jean-Michel Moutin (STMicroelectronics)
-"Implementing Different Power Features in an IP" by Sayandeep Nag (Synopsys )
-"COMSIS 802.11n: an IP to reuse - a flexible platform for design" by Roxana Ojeda (COMSIS)
-"Wired Interface IP: and the winner is..." by Eric Esteve (IPnest)
-"A Pipelined Multiprocessor SoC Design Methodology for Streaming Signal Processing" by Chen Ching-Han (National Central University)
-"Efficient ASIP Design Methodology" by Selim Zoghlami (CEA - LIST)
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European SystemC User's Group Meeting
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| 18:45 - 20:00
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Cocktail |
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SoC DAY: Wednesday December 2, 2009
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7:30 - 8:45
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Breakfast
and Registration
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AUDITORIUM |
| 8:45 - 9:00 |
Welcome
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9:00 - 9:45
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Keynote Talk: Keynote Talk: Building High-performance lower power media-intensive consumer products isn't easy!
By Michael Dimelow
Director of Marketing, Processor Division
ARM
Building High-performance lower power media-intensive consumer products isn't easy!
By Michael Dimelow, Director of Marketing, Processor Division, ARM
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| 9:45 - 10:30 |
Keynote Talk: Keynote Talk: Prototyping Using IP at Multiple Abstraction Levels Enables Embedded Software Development
 By Joachim Kunkel
Vice President and General Manager, Solutions Group
Synopsys
Prototyping Using IP at Multiple Abstraction Levels Enables Embedded Software Development
By Joachim Kunkel, Vice President and General Manager, Solutions Group, Synopsys
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| 10:30 - 11:00
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Break
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AUDITORIUM |
KILIMANDJARO
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MONT
BLANC
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MAKALU
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| 11:00 - 12:30
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Panel: How to do volume scalable chip designs in a cost conscious environmentPanel: How to do volume scalable chip designs in a cost conscious environment
Moderator:
Paul Dempsey
Editor-in-Chief
EDA Tech Forum Journal
Panelists:
- Kalar Rajendiran, Senior Director, Marketing, eSilicon
- Hal Barbour, President, Cast
- Helena Krupnova, STMicro
- Frederic Aubrun , Lattice
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Session: IP Quality & ValidationSession: IP Quality & Validation
Chairman: Dr. Jürgen Haase (edacentrum GmbH)
-"Low Power Verification of Connectivity IP cores A USB HS-OTG case study " by Sriram Balasubramanian (Synopsys)
-"Reaching 80% in Only Days: OVM Verification IP Makes Your SystemVerilog Verification Significantly More Productive" by Mirit Fromovich (Cadence Design Systems)
-"Application Specific IP – Ensuring Semiconductor IP Quality" by Gerardo Nahum (Rosetta IP)
-"A RTCA-DO-254 COMPLIANT DEVELOPMENT PROCESS FOR SUPPORTING THE DESIGN OF HIGH-QUALITY HARD-IP-CORES" by Patricia Lira (UFPE)
-"What is in you SVA? - Assertion Visualization Case Studies" by Jiang Long (Mentor Graphics Corp)
-"Software Architecture for IP verification in Operating System environment" by Ravi Kumar Vydadi (Samsung India Software Operations)
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Seminar: The future of Computing: Massively Parallel ComputingSeminar: The future of Computing: Massively Parallel Computing
Organizer:
 Nguyen Huy-Nam
Bull S.A.S./METASymbiose S.A.S
Speaker:
- Prof. Alain Grainer, UPMC/Lip6
- Frédéric Pétrot, TIMA
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Workshop
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| 12:30 - 13:30
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Lunch
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| 13:30 - 15:00 |
Panel: Transactors: where the virtual world meets the implementation worldPanel: Transactors: where the virtual world meets the implementation world
Moderator:
 Laurent Ducousso
Verification Manager
ST
Panelists:
- Heiko Mauersberger, Synopsys
- Antoine Perrin, ST
- Kenneth Larsen, Mentor
- Luc Burgun, EVE
- Tim Kogel, CoWare
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Session: Performance Evaluation & VerificationSession: Performance Evaluation & Verification
Chairman: Phil Dworsky, Director, strategic alliances (Synopsys )
-"Traffic Management for Optimizing Media-intensive SoCs" by Time Mace (ARM)
-"Performance Measurements of Synchronization Mechanisms on 16PE NOC Based Multi-core with Dedicated Synchronization and Data NOC " by Guangye Tian (ENSTA ParisTech)
-"Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device" by Yasue Nagumo (The University of Aizu)
-"TOWARDS ACCELERATING LOW-LEVEL VISION IN ROBOTICS" by Gianna Araújo (UFRN)
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Workshop
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| 15:00 - 15:30 |
Break |
| 15:30 - 17:00
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Panel: Design and Reuse -The impossible dream?Panel: Design and Reuse -The impossible dream?
Moderator:
 Jack Browne
Senior Vice President, Sales and Marketing
Sonics
Panelists:
- Arthur Marris, Cadence Design Systems
- James Aldis, Texas Instruments
- Stefano Ravaglia, SoC R&D Director, Computer System Division, STMicroelectronics
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Session: System Debugging & ModellingSession: System Debugging & Modelling
Chairman: Pankaj Singh (Infineon)
-"Low Pin-count Debug Interfaces for Multi-device Systems" by Michael Williams (ARM Limited)
-"Accelerating the development of TLM-2.0 models using MAK’s" by Markus Willems (Synopsys)
-"Transaction Analysis and Debug across Language Boundaries and between Abstraction Levels" by Rich Edelman (Mentor Graphics)
-"Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment " by Ireneusz Sobanski (Evatronix S.A.)
-"A Coverage-Driven Verification Methodology to Efficiently Increase the Quality of IP" by Gaurav Kumar Verma (Mentor Graphics)
-"Methodology for Rapid Development of Loosely Timed and Approximately Timed TLM Peripherals" by Mukundan Kadambi Narasimhachar (MindTree Ltd)
-"ABQ: Assertion Based Qualifier Methodology for Pre Existing Environment" by Krishnan Ramakrishnan (Samsung India )
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Invited Talk: Invited Talk: Memory Management
 By Niall Murphy
Memory Management
By Niall Murphy
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Workshop
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| 17:00 - 17:15
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Break |
| 17:15 - 18:45
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Panel: Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?Panel: Debug and optimisation of embedded software & SoC designs: can scalable on-chip system visibility be delivered cost-effectively?
Moderator:
 Michael Dimelow
Director of Marketing, Processor Division
ARM
Panelists:
- Serge Poublan, Product Marketing Manager, CoreSight Program Manager, ARM
- Rolf Kuehnis, Nokia
- Stephan Lauterbach, Lauterbach
- Gary Swoboda, Texas Instrument
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Session: MultiprocessingSession: Multiprocessing
Chairman: Fabien Clermidy (CEA-LETI)
-"Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm" by Gerard BOUDON (IBM)
-"PP: an application-specific processor for manycore architectures" by Lorenzo Di Gregorio (Lantiq)
-"Evaluation Evaluation of Fat-Tree Based System-on-chip Interconnection Architectures" by Azeddien Sllame (AlFateh University)
-"Scalable Architecture for Multiprocessor Design " by Ravikumar Nayagam (HCL Technologies )
-"A Novel Mesh Architecture for On-Chip Networks" by Midia Reshadi & Maryam Bahamani (Science and research branch of Azad university)
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Invited Talk: Invited Talk: Innovation by Cooperation in Embedded Signal Processing Systems
 By Peter Simkens
Managing Director
DSP Valley
Innovation by Cooperation in Embedded Signal Processing Systems
By Peter Simkens, Managing Director, DSP Valley
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Workshop
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| 19:00 - 22:00
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Banquet |
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EMBEDDED SYSTEM DAY: Thursday December 3, 2009
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7:30 - 8:45
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Breakfast
and Registration
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AUDITORIUM |
8:45 - 9:30
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Keynote Talk: Keynote Talk: Embedded Software - Technologies and Trends
 By Bernard Candaele
Deputy Director Embedded Systems TBU
Thales
Embedded Software - Technologies and Trends
By Bernard Candaele, Deputy Director Embedded Systems TBU, Thales
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AUDITORIUM |
KILIMANDJARO
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MONT
BLANC
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MAKALU
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| 9:30 - 10:15 |
Keynote Talk: Keynote Talk: Challenges and Opportunities for Multiple OS Architecture
 By Colin Walls
Mentor Graphics
Challenges and Opportunities for Multiple OS Architecture
By Colin Walls , Mentor Graphics
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Invited Talk: Invited Talk: High Level Modeling and Verification for IP-Based Systems
By Kathryn Kranen
President and CEO
Jasper Design Automation
High Level Modeling and Verification for IP-Based Systems
By Kathryn Kranen, President and CEO, Jasper Design Automation
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Invited Talk: Invited Talk: Embedded User interface: Top Ten Usability Mistakes
By Niall Murphy
Embedded User interface: Top Ten Usability Mistakes
By Niall Murphy
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Texas Instruments BeagleBoard Workshop
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| 10:15 - 10:45
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Break
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| 10:45 - 12:15
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Panel: System IP on FPGA: Challenges and IssuesPanel: System IP on FPGA: Challenges and Issues
Moderator:
 Dick Selwood
Panelists:
- Phil Dworsky, Director, strategic alliances, Synopsys
- Bernard Candaele, Deputy Director Embedded Systems TBU, Thales
- Jack Browne, Senior Vice President, Sales and Marketing, Sonics
- Jason Polychronopoulos, Manager of Verification IP Solutions, Mentor Graphics
- Gabriel Pulini, Vice President Sales EMEA, Abound Logic
- Brent Przybus, Director of Product Marketing, Xilinx, Inc.
- Jacques Cesbron, Western Europe Director, Altera
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Session: Embedded SoftwareSession: Embedded Software
Chairman: Oliver Bringmann (FZI )
-"Metric Driven Validation, Verification and Test of Embedded Software " by Markus Winterholer (Cadence)
-"Dynamic Memory Allocation and Fragmentation in C and C++" by Colin Walls (Mentor Graphics)
-"Improving Software Development and Verification Productivity Using Intellectual Property (IP) Based System Prototyping" by Frank Schirrmeister (Synopsys)
-"Android, Linux and Real-Time Development for Embedded Systems" by Colin Walls (Mentor Graphics )
-"Software FMEA and Software FTA – An effective tool for Embedded Software Quality Assurance " by Chitra T (Mahindra Satyam)
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Seminar: Computational Models for Embedded Software Seminar: Computational Models for Embedded Software
Organizer:
Huy-Nam Nguyen
Bull S.A.S.
Speaker:
- Fabrice Lemonnier, Thalès
- Peter Marwedel, Technische Universität Dortmund, Germany
- Eyal Bergman , Director of Product Marketing , CEVA
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Texas Instruments BeagleBoard Workshop
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| 12:15 - 13:00
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Lunch
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| 13:00 - 14:30 |
Panel: R&D in Europe teams up to master future system designPanel: R&D in Europe teams up to master future system design
Moderator:
 Jurgen Haase
edacentrum GmbH
Panelists:
- Brieuc Turluche , CEO , Coupling Wave Solutions
- Ivan Ring Nielsen, Technoconsult
- Volkan Esen, Infineon
- Jacques Dulongpont, Office Director, CATRENE
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Session: Embedded Systems Design & DebugSession: Embedded Systems Design & Debug
Chairman: Antonio-Marcello COPPOLA (STMicroelectronics)
-"Source Code Analysis in an Agile World" by Gwyn Fisher (Klocwork)
-"A Developer’s Perspective of PLC Configuration and Programming using FBD and ST" by Gopinath Karmakar (Bhabha Atomic Research Centre)
-"DDGEN: An Automated Device Driver Generation Tool for Embedded Systems" by Sandeep Pendharkar (Vayavya Labs)
-"Adopting a Power Management Framework for Optimized Embedded Systems Design" by Emmanuel Petit (Mentor Graphics )
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Session: Embedded SystemsSession: Embedded Systems
Chairman: Lucille Engels (Dolphin Integration)
-"NAND Flash memory in Embedded Systems" by Michal Jedrak (EVATRONIX SA)
-"Reusable Device Simulation Models for Embedded System Virtual Platforms" by Zeeshan Anwar (Mentor Graphics )
-"FUNCTIONAL-ORIENTED PROCESSORS AND PARALLEL DATA PROCESSING IN INTEGRATED NAVIGATION SYSTEMS" by nick lookin (Institute of Engineering Science)
-"Selecting an embedded MCU: How to avoid evaluation trap?" by Didier Maurer (Dolphin Integration)
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ARM Sponsored Session
mbed - Rapid Prototyping with Microcontrollers
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| 14:30 - 16:00
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Invited Talk: Invited Talk: From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?
 By Jacques Benkoski
Venture Partner
USVP (Executive Chairman, Synfora)
From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?
By Jacques Benkoski, Venture Partner, USVP (Executive Chairman, Synfora)
Panel: From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?Panel: From Processors to FPGAs to SoCs ? what are the best solutions to program algorithms onto hardware?
Moderator:
Jacques Benkoski
Venture Partner
USVP (Executive Chairman, Synfora)
Panelists:
- Brent Przybus, Director of Product Marketing, Xilinx, Inc.
- Christophe Bianchi, General Manager for Europe, Middle East and India, Synfora
- Doug Amos, Business Development Manager, Solutions Marketing, Synplicity Business Group, Synopsys, Inc.
- Pascal Urard, System Design Director, ST Microelectronics
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Session: Forum on DesignSession: Forum on Design
Chairman: Hein van der Wildt, President & CEO (Fenix Design Automation )
-"Finite Impulse Response Neural Networks with Applications in Speed Control of DC Motor Drive." by El said Sallam (faculty of engineering)
-"Continuous integration of complex reconfigurable systems " by Philippe Faes (Sigasi)
-"Evolving to a Total IP Solution to accelerate SoC Design" by Somnath Viswanath (Arasan Chip Systems Inc)
-"Practical case: Embedded Multiprocessor Design on a Flexible Hardware: NEO_CORE_CYCLONE_III" by Thierry DECHANDON (ADENEO)
-"Scatter-Gather DMA IP Core for PLDA EZDMA IP" by Dmitry Smekhov (Instrumental Systems)
-"Generating timing models for full custom analog or mixed signal design to enable IP reuse" by Basudeva Dash (Infineon Technology)
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Seminar: TLM Verification for Systems-on-ChipSeminar: TLM Verification for Systems-on-Chip
Organizer:
 Oliver Bringmann
FZI
Speaker:
- Volkan Esen, Michael Velten, Wolfgang Ecker, Infineon Technologies
- Marcio Oliveira, Markus Becker, Wolfgang Mueller, Henning Zabel, University of Paderborn/C-LAB
- Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, University of Tübingen
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Workshop
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