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Keynote Talk: Strategies for Managing SoC IP Risks at Advanced Process Nodes
Tuesday December 1, 2009, 9:45 - 10:30 | Room: Auditorium
By Yervant Zorian, Vice President & Chief Scientist
Virage Logic

As we navigate through the nanometer landscape, the SOC manufacturability challenges are tremendous. The impact of advanced process nodes on yield, reliability and time to volume is forcing managers to select IP solutions that eliminate the risks and helps ensure optimum yield, superior quality and greater reliability. This presentation discusses today’s SOC challenges and introduces strategies to manage IP risk, as we navigate through the new process nodes.

Biography:

Dr. Yervant Zorian has served as Virage Logic’s Vice President and Chief Scientist since joining the company in 2000. Prior to that, Dr. Zorian served as a Distinguished Member of the Technical Staff at AT&T, Bell Laboratories and Chief Technical Advisor to LogicVision.

Dr. Zorian also serves as the Vice President of the IEEE Computer Society for Conferences and Tutorials and is the Editor-in-Chief Emeritus of IEEE Design & Test of Computers. He founded and presently chairs the IEEE 1500 standardization working group for embedded core test, holds 20 US Patents and has authored over 250 papers and four books. Dr. Zorian has received a number of best paper awards, is an Honorary Doctor of the National Academy of Sciences of Armenia, is a Fellow of the IEEE, is the recipient of the 2005 IEEE Industrial Pioneer Award, and the 2006 recipient of the IEEE Hans Karlsson Award.

Dr. Zorian received a MSc degree from the University of Southern California, and a Ph.D. from McGill University.