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Panel: How to do volume scalable chip designs in a cost conscious environment
Wednesday December 2, 2009, 11:00 - 12:30 | Room: Auditorium

The use of ASICs in low volume production has always been a marginal value proposition, and this problem has been compounded as the definition of _low volume_keeps climbing as Moore s law drives up the cost of mask sets. Several approaches have been taken to address this. Fabless providers aim at covering this niche with full custom ASICs at lagging process nodes. Structured ASIC providers attempt to overcome mask costs by abbreviating the number of design masks. FPGA vendors approach the problem either through the use of high-end FPGAs with ASIC migration paths or by providing FPGAs that are inherently low cost & low power

Chairperson:

		Paul Dempsey Editor-in-Chief EDA Tech Forum Journal
	Paul Dempsey is Editor-in-Chief of EDA Tech Forum Journal and a senior US correspondent for E&T, the magazine published by the Institution of Engineering & Technology. He has been working in the technology sector for almost 20 years, contributing to publications such as EETimes, Red Herring, and specialist newsletters published by the Financial Times.

Panelists:

		Kalar Rajendiran Senior Director, Marketing eSilicon
	The use of ASICs in low volume production has always been a marginal value proposition, and this problem has been compounded as the definition of “low volume” keeps climbing as Moore’s law drives up the cost of mask sets. Several approaches have been taken to address this. Fabless providers aim at covering this niche with full custom ASICs at lagging process nodes. Structured ASIC providers attempt to overcome mask costs by abbreviating the number of design masks. FPGA vendors approach the problem either through the use of high-end FPGAs with ASIC migration paths or by providing FPGAs that are inherently low cost & low power.
		Hal Barbour President Cast
	Hal earned a BSEE and worked several years as a circuit designer, before moving on to technical sales and marketing positions with GenRad, Intergraph, and HHB Systems (later acquired by Racal-Redac). Witnessing both stunning successes and colossal managerial failures, he has applied those lessons to leading semiconductor intellectual property provider CAST, Inc. the past several years. Pioneering a successful virtual and distributed organization model and using a lean, customer-oriented operations philosophy, Hal has helped CAST succeed and thrive in a volatile and challenging market.
		Helena Krupnova STMicro
	Helena Krupnova is a verification/FPGA prototyping expert at ST Microelectronics. She is part of the Functional Verification Team within the System Platform and Tools group/HED. She leads the FPGA prototyping activity since november 2000. She has built the FPGA prototypes for about 20 high-complexity ST SOC projects in the domains of multimedia, telecommunications, automotive, etc. Helena obtained a PhD from the INP Grenoble in 1999 in the domain of FPGA prototyping. She obtained the MSc degree from UJF/Grenoble (1996) and from Tallinn Technical University, Estonia (1993). She has her computer science engineering diploma from Tallinn Technical University in 1991.
		Frederic Aubrun Lattice