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Panel: Improving IP Quality vs. Losing Design Productivity - What Are the Tradeoffs?
Tuesday December 1, 2009, 17:15 - 18:45 | Room: Auditorium

When time-to-market and cost reductions dominate IP design and integration, instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers. This panel will use real world examples from IP buyers and sellers to address questions like: How do you balance the cost of addressing IP quality up front vs. after tape-out ? Where do semiconductor companies and IP vendors usually set the cursor? What are the most important quality issues to address? How helpful are the quality standards in addressing key issues? Is there any way to reduce the impact of quality management on design schedules and costs?

Chairperson:

Phil Dworsky Synopsys

Panelists:

		François Rémond Director, CAD & Design Methodology STMicroelectronics
	Francois Rémond was born in 1956 in Paris (France). He received a Master Degree of Engineering sciences from INSA Rennes in 1979. He joined BULL in 1981 then THOMSON-CSF in 1982, which became then STMicroelectronics. Since 2003, he is CAD & Design Methodology Director at the Home Entertainment & Displays Group of STMicroelectronics, supporting design activity in France, UK, India and USA.
		Philippe Di Crescenzo Director of Engineering Arteris
	Philippe di Crescenzo is Director of Engineering at Arteris. Philippe started 20 years ago as ASIC designer at Intel. He has then held various technical management positions at Synopsys and TransEDA. He received his Microelectronics Engineering Degree from ISIM, Montpellier.
		Kathryn Kranen President and CEO Jasper Design Automation
	Kathryn Kranen is responsible for leading Jasper’s team in successfully bringing the company’s pioneering technology to the mainstream design verification market. She has 20 years EDA industry experience and a proven management track record. While serving as president and CEO of Verisity Design, Inc., US headquarters of Verisity Ltd., Kathryn and the team she built created an entirely new market in design verification. (Verisity later became a public company, and was the top-performing IPO of 2001.) Prior to Verisity, Kathryn was vice president of North American sales at Quickturn Systems. She started her career as a design engineer at Rockwell International, and later joined Daisy Systems, an early EDA company.
		Michel Tabusse Co-founder, president & CEO Satin IP Technologies
	Prior to starting Satin IP Technologies, Michel Tabusse was with Synopsys, director of business development for telecom IP products, then in charge of IP and services sales to major semiconductor companies. Before Synopsys, Michel was founder and general manager at Arcad SA until acquisition by Synopsys in 1994. Michel has a degree in Engineering and a PhD in Microelectronic Design (LIRMM).
		Joachim Kunkel Vice President and General Manager, Solutions Group Synopsys
	Joachim Kunkel joined Synopsys in 1994 and is currently vice president and general manager of the Solutions Group. In that capacity, he manages the business units responsible for Synopsys DesignWare® intellectual property (IP), strategic market development and system-level design. Before coming to Synopsys, Mr. Kunkel was co-founder of CADIS GmbH in Aachen, Germany. There, he served as managing director and performed myriad duties in engineering, sales and marketing. Before co-founding CADIS, Mr. Kunkel was a research assistant at the Aachen University of Technology, where he conducted research in system-level simulation techniques for digital signal processing, with special emphasis on parallel computing. Mr. Kunkel holds an MSEE degree, the Dipl.-Ing. der Nachrichtentechnik, from the Aachen University of Technology.