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Panel: IP Reuse vs. IP Leverage: What's the difference, and what are the issues?
Tuesday December 1, 2009, 11:00 - 12:30 | Room: Auditorium

Especially in this economy, IP deployment is critical for time to market and reduced development costs. However, there is a huge difference between reusing IP (as is), and leveraging IP (with modifications.) What are the issues for IP reuse and IP leverage? How can IP be more easily consumed? Explored? Comprehended? Modified successfully, and then verified? Is IP transfer a transfer of technology, design knowledge , or design flow? How can verification IP be improved? IP quality? What solutions are coming from the IP and EDA vendor ecosystem?

Chairperson:

		Kathryn Kranen President and CEO Jasper Design Automation
	Kathryn Kranen is responsible for leading Jasper’s team in successfully bringing the company’s pioneering technology to the mainstream design verification market. She has 20 years EDA industry experience and a proven management track record. While serving as president and CEO of Verisity Design, Inc., US headquarters of Verisity Ltd., Kathryn and the team she built created an entirely new market in design verification. (Verisity later became a public company, and was the top-performing IPO of 2001.) Prior to Verisity, Kathryn was vice president of North American sales at Quickturn Systems. She started her career as a design engineer at Rockwell International, and later joined Daisy Systems, an early EDA company.

Panelists:

		Sanjay K. Srivastava President, CEO Denali
	Sanjay Srivastava has over fifteen years of experience in the EDA and semiconductor IP industries. Before co-founding Denali, Mr. Srivastava was the director of engineering at Vantage Analysis Systems. Mr. Srivastava holds an MSEE from the University of Illinois at Urbana-Champaign and a B.Tech in Electrical Engineering from the Indian Institute of Technology, Kanpur.
		Andrea Fortunato European Director of Professional Services Numetrics
	Andrea Fortunato is the European director of professional services for Numetrics Management Systems Inc., where he has helped some of the semiconductor industry’s leading companies improve their R&D productivity. He’s responsible for introducing, deploying and supporting Numetrics software products for potential customers and existing European key accounts. Before joining Numetrics in November 2007, Mr. Fortunato spent much of the past two decades in key roles at ST Microelectronics in Europe and North America. Among his positions at ST, Mr. Fortunato was program control manager ST’s Crolles, France, facility, where he helped define, create and deploy project-management core practices and the associated IT system throughout technology platforms. Mr. Fortunato also was design support manager for ST ASIC and COT designs in Ottawa, Canada, and also served as the ST project leader and resident engineer for Nortel in Ottawa. Prior to his work with ST, he was CAD support engineer at Philips in Paris and semi-custom design engineer at Aurel Semiconductor, in Bologna, Italy. He holds a degree in electronics engineering from the University of Bologna with a specialization in microelectronics. His long focus on making semiconductor and system design more productive stretches back to this thesis: “Impact of Custom and Semi-Custom Circuits on Design Methodologies: Gate Array Design of a Lift Controller,” which he completed in 1985.
		Olivier Haller STMicroelectronics
	Olivier Haller is the manager of the Design Verification Team in the Functional Verification Group at STMicrelecronics. He is responsible for the definition and deployment of dynamic verification methodologies at ST, including support for key ST projects. Mr. Haller started his carreer at ST in 1998 as digital designer for wireless products. In 2000 he pursued functional verification as member of the CAD support team, introducing coverage-driven verification techniques. Since 2004 he is leading the dynamic verification team in ST s central verification group where he has been pioneering the introduction of functional qualification within ST to qualify IPs and improve verification environements. Mr. Haller is graduated from Grandes Ecoles d ingénieur en électronique in Grenoble and holds a joint ENSERG/ENSIMAG engineering degree in electronics and computer science.