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Panel: System IP on FPGA: Challenges and Issues
Thursday December 3, 2009, 10:45 - 12:15 | Room: Auditorium

IP reuse on FPGA at a low level has been stated as viable and moreover proved to be very successful.
This panel addresses the Reuse of System IP especially when having to migrate from a platform to a next one.
Are ESL methodologies applicable? Are there specific infrastructures needed to make this Reuse work?
As system integration needs to cope with application level requirements, special attention has be given to low power, safety, QoS, reliability, security : these constraints will be commented by the panelists ...

Chairperson:

		Dick Selwood
	Dick Selwood is Europe Editor for Techfocus Media, contributing to IC Design and Verification Journal, FPGA Journal and Embedded Technology Journal, and is a contributing editor to the UK's Components in Electronics. He has worked in the semiconductor industry for over 30 years, in PR and in journalism, including work with IDMs, test and measurement, EDA and FPGA companies and in the embedded industry.

Panelists:

		Phil Dworsky Director, strategic alliances Synopsys
	Phil Dworsky is a veteran of 25 years in EDA and IP. Having joined Synopsys in 1993, he is currently director, strategic alliances. Prior to his current position, Mr. Dworsky held management positions in marketing, technical marketing and corporate applications at Synopsys, most recently as director, marketing and applications for DesignWare IP. Mr. Dworsky came to Synopsys from Performance Processors, a parallel processing company, where he was co-founder and principal engineer. Before that, he was a co-founder of Silicon Solutions/Zycad, an early provider of simulation acceleration technology. He started his career at Hewlett-Packard as a hardware and software designer. Mr. Dworsky holds a Bachelor of Science degree with high honors in EECS (electrical engineering and computer science) from Princeton University.
		Bernard Candaele Deputy Director Embedded Systems TBU Thales
	Bernard Candaele is the Deputy Director of the Embedded Systems Technical Business Unit at Thales. After a first experience at Intel, Chandler and at Cimatel, Paris (Common design center for Intel/Matra-Harris) as microprocessor IC designer and project leader for automotive and telecom micro-controllers, he has been with Thomson-Csf since 88. He has been program leader for Thomson ASICs and then had several managing and technical responsibilities inside the company. He has competencies in SoC projects for telecom, multimedia and security related products, in developing new digital processing architectures and platforms, in managing EDA solutions for embedded electronics development, and in R&D activities in co-operation within European and National programs. Bernard Candaele is a Steering Board Member of Thales Hardware R&D domain, a Thales senior expert, an IEEE member and he is author or co-author of more than 50 papers.
		Jack Browne Senior Vice President, Sales and Marketing Sonics
	Jack Browne is Sonics’ senior vice president of sales and marketing. Prior to joining Sonics, Mr. Browne served in several executive roles at MIPS Technologies, including executive vice president of worldwide sales and executive vice president of marketing. Earlier in his career, he was the head of Motorola’s 68000 processor marketing team. An acknowledged industry spokesman, Mr. Browne has written more than 100 papers for industry publications and presented at more than 100 industry conferences. He holds a B.S.E.E. degree from the University of Texas.
		Jason Polychronopoulos Manager of Verification IP Solutions Mentor Graphics
	Jason Polychronopoulos is responsible for verification IP solutions, which includes the Questa MVC product line, at Mentor Graphics. Jason came to Mentor from SpiraTech, which was acquired by Mentor in 2006. There he worked on development, marketing and deployment of the company's automation technology for verification IP. Prior to this, Jason worked as an ASIC design engineer, having obtained an MEng honours degree in electrical engineering from the University of Manchester, United Kingdom.
		Gabriel Pulini Vice President Sales EMEA Abound Logic
	Gabriel Pulini joined Abound Logic in 2004 . He's a sales, marketing and business development executive with 25 years of diversified experiences across the Automatic Test Equipment, Electronic Design Automation and FPGA industries. With his extensive international customer experience, he has contributed to the successful introduction of new products to different markets. Prior to Abound Logic, Gabriel was Marketing Director at Mentor Graphics. He started his career as a research engineer at Alcatel in Italy, and later joined Teradyne. Gabriel is currently a member of the executive management team in Abound Logic where he has contributed to the growth of the company with its strategic expansion from an embedded FPGA IP provider to a player in the high density FPGA device market
		Brent Przybus Director of Product Marketing Xilinx, Inc.
	Brent Przybus is director of product marketing with responsibility for global product introductions and marketing campaigns for the company's current and next-generation flagship Virtex and Spartan FPGA products. Przybus joined Xilinx in 2001 and has over 15 years of marketing and engineering experience in the programmable logic industry. Prior to joining Xilinx, Przybus worked as an engineering manager in the advanced graphics and high-performance computation industries with Evans & Sutherland and LinuxNetworx, where he designed systems based on programmable logic to implement advance simulation environments and accelerators for data intensive computation. Przybus has authored, published and presented globally in conferences, journals, and trade publications. Przybus holds a BS in computer engineering from the University of Utah in Salt Lake City, Utah and a MBA from Westminster College in Salt Lake City, Utah.
		Jacques Cesbron Western Europe Director Altera
	Jacques Cesbron is Western Europe Sales Director for Altera Western. Jacques Cesbron has been with Altera for five years and ccupied previously sales managing position for Altera Telecom customers. Mr Cesbron started his career at Thomson then at Lucent in IC designs for telecommunications equipments then in upstream purchasing functions, then he moved in the sales as product manager at MEMEC. Mr Cesbron has a Telecom Engineering degree at ESEO and a master in business from ESCP / EAP Paris.