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Short Facts about IP/SoC 2004



IP/SOC 2005 presentations are available online at
www.us.design-reuse.com/ipbasedsocdesign/2005

Welcome

IP/SOC 2005 (IP Based SoC Design) will be the 14th edition of the Working conference on hot topics in the design world, focusing for the past 5 years on IP based SoC design and hold in the well known Silicon and Alliance Nanometer Valley in the French Alps.

Working conference

  • Keynote talks
  • Six Keynote talks are planned, namely:



    "Successful IP Business Models"
    Doug Pattullo, Technical Director
    TSMC Europe BV
          


    Tomorrow's Challenges for Today's IP Providers"
    Keith Clarke, VP of Technical Marketing
    ARM (U.K)



    "Branding the Architecture of a Microprocessor"
    Carl Schlachte, President and CEO
    ARC International



    "Selling the Family Jewels: Can IP Flourish in a Fabless Chip Company?"
    Rob Tobias, Director of IP Marketing
    Silicon Image



    "SoC/IP Market Overview and Outlook"
    Jim Tully, VP Distinguished Analyst
    Gartner Dataquest


    "China's Silicon IP core, the status and future development"
    Du Jiao
    Vice General Manager of Marketing, IC Division
    CSIP

    Keynote talks Chairman: Paul Miller, Senior Vice President and Group Director, CMP Media Electronics and Software Development Groups

  • Panels
  • A set of very hot panels are planned, and addressing the following topics:


      The IP challenge in industry
       
      Moderated by: Ron Wilson (EETimes)
      Panelists:
           - Douglas Pattullo, Manager Technical Support, TSMC
           - Philippe Decamp, Strategic Business Manager, Europe,Denali Software, Inc.
           - Harmel Sangha, Director of CoreWare® IP Marketing, LSI Logic
           - Kenneth Larsen, Technology Marketing Manager, 0-In verification Business, Mentor Graphics

      EEtimes is conducting a market research on this topic over the next 4 months and the conclusion will be the topic of the panel commented by industry representatives
      EE Times readers are under increasing time-to-market pressures in today’s market. In order to meet these shrinking schedules, they are learning to reuse internal IP and buy external IP in order to reduce total design time.
      This Industry Challenge will research and report on the difficult decisions designers are facing and offer possible solutions.



      How Brand enables companies to be more competitive in today’s global SoC industry

      Moderated by: Ron Wilson, EETimes
      Panelists:
           - Carl Schlachte, President & CEO, ARC International
           - Tim Messegee, VP Corporate Marketing, Rambus
           - Keith Clarke, VP of Technical Marketing, ARM
           - Jack Browne, VP of marketing, MIPS Technologies
           - Jim Tully, VP Distinguished Analyst, Dataquest
           - Chet Silvestri, CEO, MoSys

      In the 21st century, “brand” has re-emerged as the fundamental means to differentiate a product in the global marketplace and generate greater margins.   However, device designers are left to choose from decades old “standards-based” IP blocks that leave little to no room for innovation.  The new trend of leveraging configurable processor technology offers a cost-effective solution where the end product is highly differentiated down to the microarchitecture of the processor itself.  Hence, SoC designers now have the ability to implement their “brand” into the hardware of a device, further increasing their competitive edge in the global marketplace.  The panel will explore this trend by offering views from varying points of the semiconductor industry food chain



      How reusable is our verification infrastructure?

      Moderated by: Sunil Kakkar, Chief Technologist – Verification, Freescale Semiconductor India Ltd
      Panelists:
           - Janick Bergeron, Synopsys
           - Kenneth Larsen, Mentor Graphics
           - Michael Lerchenmuller, Cadence
           - Simon Johney, Wipro
           - Warren Savage, IPextreme
           - Mark Hampton, Certess
           - Rich Faris, Real Intent, Inc.
       
      A large percentage of the total SOC design and verification effort is spent on redesigning the entire verification environment as we move through the following stages (System model architecture studies, Unit/Block level design, External IP integration, Chip level design, Emulation

      The block level test benches and patterns do not flow seamlessly into chip level verification and emulation cannot reuse these test benches if they are not synthesizable.
      Further, RTPG strategies cannot reuse many of the monitors, drivers and response checkers developed for directed tests.  The verification environment for external IP is also not standardized and hence does not flow seamlessly into the existing environment.

      A distinguished panel of industry experts and luminaries will discuss if the verification and validation cycle can be made more effective by ensuring a standardized, high quality, efficient and a modular verification reuse environment?



      Enabling Technologies for Advanced SoC Design:  IPs and vertical kits
       
      Moderated by: Tim Daniels, LSI logic
      Panelists:
           - Daniel Vellou, Leti/CEA
           - Gary Delp, LSI logic
           - Roddy Urquhart, Synopsys
           - Eric Dupont-Nivet, CSO and Co-Founder, Soisic
           - Tim Barnes, VP of Marketing Europe, Cadence
           - Jim Venable, Mentor Graphics
           - Zvi Or-Bach, President and CTO, eASIC

      The implementation of Advanced System-On-Chip (SoC) is becoming an ever more complex task. On the manufacturing side meeting process rules, test and yield control is no longer straightforward. On the IP side integrating tens, even hundreds of IP blocks on a single chip, some of them high-speed interfaces, mixed signal or RF all add complexity and risk. On the technology side ultra-thin line widths and the increasing impact of interconnects causes ever more issues controlling placement and timing closure.



      Verification IP for IP Verification: Who is leading whom ?

      Moderated by: Chris Lennard, ARM
      Panelists:
           - Joachim Kunkel, VP Engineering, Synopsys
           - Kenneth Larsen, Mentor Graphics
           - Eric Esteve, PLDApplications
           - Aleksandar Randjic, HDL Design house
           - Michael Lerchenmuller, Cadence


      A smaller number of higher-quality IP providers is a sign of a maturing IP ecosystem, but are the customers willing to pay the price for quality? For complex interfaces like PCI Express, SATA, and even DDR-SDRAM, its clear that the verification IP is more complex than an instance of design IP. In this panel, three IP providers and three IP consumers will discuss the growing role of verification IP for improving IP quality, and the technical and economic factors that are necessary to enable an effective IP ecosystem.



      How to protect IP in the “new world?” and what business models can protect IP the best?

      Moderated by: Jim Tully, VP Distinguished Analyst, Gartner Dataquest
      Panelists:
           - Gary Delp, CTO, VSI Alliance
           - Ralph von Vignau Chairman SPIRIT Consortium, CTO, Philips Semiconductors
           - Grant Martin, Chief Scientist, Tensilica
           - Ken Wagner, Director, PMC Sierra

      As new geographic regions begin to develop “home-grown” facilities for IP development and integration, IP use and misuse has risen as a top issue facing IP providers and users alike. Panelists representing IP visionary organizations (VSIA, Spirit), along with IP developers and integrators will look at some of the issues surrounding current and potentially future methods of protecting IP from theft. Are current methods adequate as IP begins to flow in and out of new countries? What needs to still be done to protect investments in IP and who should be responsible for the creation of IP protection mechanisms? Can the IP market sustain many providers in an eco system governed by standards? Will industry standards enable the creation of a profitable IP market. How will modern tools and development methods effect the IP market




      Accessing the Value of the Small IP Provider in Today’s Chip Industry

      Moderated by: Jim Lipman, Contributing Editor, TechOnLine and SOCcentral
      Panelists:
           - Nabil Takla, Ceo of Innovative Semi.(IP provider)
           - Charles Ng, VP Worldwide Marketing, Kilopass Technology (IP provider)
           - George Janac, Founder & Executive Chairman, Giga Scale IC
           - Jim Tully, Gartner/Dataquest (semiconductor research analyst)
           - Doug Patullo, Technical Director, TSMC Europe BV
           - Peter Hirt, Director of IP Partnerships and Procurement, STMicroelectronics

      This panel, representing small IP providers, IP integrators, silicon foundries, and the semiconductor analyst community, will debate the role of the small IP vendor in current and future semiconductor markets.  Our esteemed panelists will also give their opinions of what the small IP vendor must do to flourish or, at least, survive in the highly competitive world of semiconductor IP. Finally, they will provide some insight into which application areas are ripe for new IP vendor participation

  • Technical Sessions
  • Click here to view detailed program

    IP/SOC 2005 best prizes

    CEA/LETI Best IP/SoC Award 2005 will be delivered under the sponsorship of CEA/LETI and the LSI IP Design Award Committee in Japan. A pre-selection process will identify the most innovative and proven design candidates.

    During the conference design experts will be able to meet the designers and get adequate information by attending a non stop, first day, poster presentation in a dedicated room he will then be able to submit a report and participate to the ballot

    Exhibition

    In addition the IP/SoC 2005 conference has an exhibition attached, giving you the opportunity to see the reality of a SOC connected world. The joint exciting dedicated exhibition will allow you to meet the most advanced suppliers and take the chance to see the last products of the best vendors including ARM, Barco Silex , Cambridge Consultants, CoWare, Delta, Design And Reuse, eASIC, EVE Corp., Ignios, IPextreme, MatrixOne, Mentor Graphics, MoSys, Novas Software, OCP-IP, Prosilog, Synopsys, Target Compiler Technologies, Temento Systems and so on..

    Book your space now.

    Around IP/SOC 2005

    • Training
      A training will take place the day before the conference on IP Delivery Best Practice.
      More details available here

    • Visit to the most advanced European IC manfacturing facilities of the 'Crolles2 Alliance'
      A visit to the most advanced European IC manufacturing facilities of the 'Crolles2 Alliance' (STMicroeletronics, Philips and Freescale) will be organized during the conference

    • Platform Modelling and Performance Analysis Workshop
      Organized by The European Chip and Systems design Initiative (ECSI)
      December 9, 2005 - Grenoble, France
      Workshop description: agenda details

    Important Dates

    Final Version of the manuscript November 12, 2005
    Working Conference December 7-8, 2005


    IP Based SoC Design Archives

    The foils of previous years' "IP / SOC" events presentations are available online :


    IP/SoC 2005
    IP/SoC 2004
    IP/SoC 2003
    IP/SoC 2002
    IP/SoC 2001
    IP/SoC 2000


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