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IP/SOC 2006 (IP-Based SoC Design) will be the 15th edition of the working conference on hot topics in the design world, focusing for the past 6 years on IP-based SoC design and held in the well known Silicon and Alliance Nanometer Valley in the French Alps.

Working Conference

Similar to the previous events, this working conference will be partitioned into technical papers, panels and invited papers, with a balanced contribution from industrial and academic participants.

Confirmed keynote talks:

		"Investment opportunities in IP" Jacques Benkoski US venture Partners
		"SoC/IP Market Overview and Outlook" Jim Tully, VP Distinguished Analyst Gartner Dataquest
		" The role of virtual fabless providers for a predictable road to product" Massimo Vanzi, CEO accent
		"Hardware Initiatives in the Open Source community" Fadi Azhari Marketing Director Sun Microsystems, Inc.

A full track of technical panelsaddressing the most challenging topics will be animated by the best worldwide specialists in the field:

• How Disruptive Technologies will Shape SoC Design and EDA Tool Development

 
Moderated by: Jim Tully, Gartner/DataQuest
Panelists:
     - Maria Gabrani, IBM Zurich Research Laboratory
     - David Fritz, Silistix
     - Phil Dworsky, Synopsys
     - Michael Sydow, Lightspeed Logic
     - Simon Davidmann, Imperas
     - Andreas Hoffmann, CoWare



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• Automated Soc Assembly-dream or reality; There ARE Solutions to the Pain of IP Integration

 
Moderated by: Richard Wallace, Editor-in-Chief, EE Times Europe
Panelists:
     - Olivier Florent, STMicroelectronics
     - Ralph Morgan, Synopsys
     - Chris Lennard, ARM
     - Dr. Satya Gupta, Open-Silicon



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• Design knowledge sharing or IP reuse? Is design reuse practical and viable in an enterprise

 
Moderated by: Richard Wallace, EEtimes
Panelists:
     - Kathy Werner, Freescale
     - David Yoon, Cisco
     - Bernard Candaele, Thalès group
     - Bill Martin, Mentor Graphics
     - Frederic Joly, TES Electronic Systems
     - Gabrièle Saucier,  Design and Reuse



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• Integrating Nonvolatile Memory in SoC Designs: Save Time and Reduce Design Costs

 
Moderated by: Jim Lipman
Panelists:
     - Larry Morrell, VP, GM IP Products, Impinj
     - Craig Rawlings, Kilopass Technology
     - Pierre Fazan, Founder & CTO, Innovative Silicon
     - Rick Shen, eMemory Technology
     - Peter B. Gillingham, Vice President and Chief Technology, Mosaid
     - Xerxes Wania, President & CEO, Sidense



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• Reconfigurable IP/SoC and power consumption

 
Moderated by: Paul Holt, Vice President of Customer Support, ARC International
Panelists:
     - Andreas Hoffman, Founder of LISATek and Engineering Director, CoWare
     - Steev Wilcox, Founder and Chief Architect, Azuro
     - Sean Redmond, Vice President of European Sales and Customer Support, Cadence
     - Yatin Trivedi, Director of Industry Partnerships, Magma
     - John Swanson , Director of IP Solutions, Synopsys
     - Jeremy Bennett, Tension



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• Network on Chip

 
Moderated by: Huy Nam Nguyen, Bull S.A.S.
Panelists:
     - K. Charles Janac, Arteris
     - Alain Greiner, UPMC/LIP6
     - David Fritz, Silistix
     - Marcello Coppola, ST-Microelectronics
     - Oliver Bringmann, FZI Forschungszentrum Informatik
     - Fabien Clermidy (CEA/Leti)



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• How to Evaluate and Choose Hard IP

 
Moderated by: Jim Lipman
Panelists:
     - Michael Kaskowitz, Senior Vice President, Semiconductor IP, Mosaid
     - Larry Morrell, VP, GM IP Products, Impinj Inc.
     - Kathy Werner, VSIA & Freescale
     - Brent Dichter, ARM
     - Mary Ann White, Virage Logic
     - Mike Kliment, Mentor Graphics



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• Design for Debug (DFD) and Design for Test (DFT)

 
Organized by: Anish Kumar (Dear Born Electronics India Bangalore)
Panelists:
     - Anthony Berent, ARM
     - Pramesh Dahiya, Integramicro System Pvt Ltd
     - Doug Goodman, Ridgetop Group
     - Michel Depeyrot, Dolphin Integration



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• Design flow integration with IP-XACT from The SPIRIT Consortium : from proof point to industrial adoption

 
Moderated by: Pierre Bricaud
Panelists:
     - Loic Le-Toumelin, SoC Development Methodology , Wireless Cellular Systems , TI
     - Gabriele Saucier, Design And Reuse
     - Wolfgang Ecker, Principal Engineer, Infineon
     - Xavier Caron, Design Flow Engineer, ATMEL

• SoC Design Platform • Chairman: Bart De Loore, NXP Semiconductors
• IP Based Architecture • Chairman: Bernard Candaele, Thales
• Collaborative Design • Chairman: Francois Kleitz, Alcatel
• IP Design • Chairman: Paolo Pezzati, Cadence
• Mixed Signal IP • Chairman: Marcello Coppola , STMicroelectronics
• IP Protection - Provider Selection • Chairman: Phil Dworsky, Synopsys
• IP Design / Physical Design • Chairman: Paolo Pezzati, Cadence
• Standard for automotive • Chairman: Warren Savage, IPextreme
• Standards and Wrappers • Chairman: Pierre Bricaud, Synopsys
• Verification • Chairman: Steve Leibson, Tensilica
• Network on Chip • Chairman: Huy Nam Nguyen, Bull
• Validation - Test • Chairman: Alain Greiner, University of Paris 6
• Protoyping • Chairman: Bill Martin, Mentor Graphics
• High level / TLM • Chairman: Chris Lennard, ARM
• Industrial approaches in Verif / Proto • Chairman: Helena Krupnova, ST Microelectronics
• High level model and design Forum • Chairman: Kathy Werner, Freescale
• Test debug Forum • Chairman: Denis Rousseau, Temento
• Design forum • Chairman: Joseph Borel, JB-R&D
• SoC Platform Forum • Chairman: Peter Gillingham, Mosaid

Click here to view detailed program

IP/SOC 2006 Best Design Paper Awards

Each year IP/SoC Conference proud to recognize the excellent, novel, innovative and highly practical design ideas that authors contribute. Excellence in design – whether it be within an IP block or a complete system continue to be the future of the IP/SoC industry. This year, in conjunction with sponsors CEA/LETI and the LSI IP Design Award Committee in Japan, it will offer two prizes to the most interesting and innovative design papers.

Papers will be judged on both the originality and practicality of the design, and the quality and presentation of the paper. Finalists will be able to take part in a poster session in the main exhibition area during the lunch and afternoon coffee break of the first day so that conference delegates can mingle and discuss the designs with the authors. Voting by delegates and judges shall take place during the first day and the two winners shall be given their awards during the prestigious conference banquet on the evening of the first day.

Around IP/SOC 2006

• "TLM Standards workshop" organised by ECSI

• "Nanometer MPSOC Design Using Configured Cores" by Steve Leibson (Tensilica, Inc.)

• " The IP-XACT Technical Awareness Session by The SPIRIT Consortium "

• "Next generation IP based Collaborative Design" by Gabrièle Saucier (D&R)

• "Training Course on Formal Verification" by Huy Nam Nguyen (Meta Symbiose)

Exhibition

In addition to the IP/SoC 2006 working conference, the attached exhibition gives you the opportunity to see the reality of a SoC connected world. The exhibition will allow you to meet the most advanced suppliers and see the latest products.

Book your space now.

Important Dates

Deadline for submission of the extended abstract Notification of acceptance Final Version of the manuscript Working Conference

September 25, 2006 October 23, 2006 November 13, 2006 December 6-7, 2006

Location

Espace Congres du World Trade Center
5 place Robert Schuman
38 000 Grenoble
FRANCE

IP/SoC Conference Archives

The foils of previous years' "IP Based SoC Design" events presentations are available online:

• IP Based SoC Design 2005
• IP Based SoC Design 2004
• IP Based SoC Design 2003
• IP Based SoC Design 2002
• IP Based SoC Design 2001