IP / SoC 2006 - Automated Soc Assembly-dream or reality; There ARE Solutions to the Pain of IP Integration

	Feedback \| D&R Products \| Site Map \| Register \| MyD&R

Silicon IP Verification IP Software IP Wanted IP !!! Free Download IP Analytics (Restricted Access) FPGA Board / Kit Design Services Foundries Main IP/SoC Products Embedded Systems Design Platform / Structured ASIC Foundries FPGA / CPLD Fabless / IDM Deals Legal Business Financial Results People ESL Design Commentary / Analysis Main Silicon IP / SoC Verification IP FPGA / CPLD Embedded Systems Design Platform / Structured ASIC ESL Design ESL Design Standards & Best Practice Structured ASIC Verification IP Main On Cores Embedded Systems EDA Tools IP Cores Tool Demos D&R Partners Research / Market Reports Events Calendar Webcasts / Podcasts Online Bookstore

Home/Introduction

Program Committee

Exhibition

Conference Program

Pratical Information

Training & Tutorials

Automated Soc Assembly-dream or reality; There ARE Solutions to the Pain of IP Integration

Moderated by:

Richard Wallace
Editor-in-Chief
EE Times Europe

Panelists:

		Olivier Florent STMicroelectronics			Ralph Morgan Synopsys
		Chris Lennard ARM			Dr. Satya Gupta Open-Silicon

Integrating just one IP core into an SoC is difficult, particularly if the core hasn’t been “qualified.” However, the integration of more than one core presents the far more difficult problem of qualifying each IP core and then making sure the cores have the “hooks” to work together.

Panelists will provide different viewpoints (IP providers, IP integrator, EDA vendor, and customer) on why IP integrator problems just “won’t go away” and on who takes responsibility for the various integration problems associated with a variety of types of IP. They will also present their ideas on how to minimize these problems