Industrial approaches in Verif / Proto

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"Industrial approaches in Verif / Proto" Session

Moderated by Helena Krupnova, ST Microelectronics
Dec. 7, 2006 - 13:15-14:35

"A Unified CPU Modeling for SoC Verification" by RAVI KUMAR AVUDAI NAYAGAM from HCL Technologies Ltd.
"Measurable Verification Methodology for Highly Configurable IP Cores" by Vishal Namshiker from Synopsys
"Verification planning for Reusable core based designs" by Anjali Vishwanath & Ranga Kadambi from Infineon Technologies Asia Pacific Pte Ltd
"Improving ASIC Design Verification using FPGAs and Structured ASICs" by Pat Mead from Altera
"An Analog Verification and IP Development Environment" by Stephan Weber from Cadence