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"IP Design" Session

Moderated by Sho Mori, IPTC Corporation
Dec. 6, 2006 - 13:30-14:45
  • "IP Core for an H.264 Decoder SoC" by Wagston Staehler from UFRGS & Altamiro Susin from UFRGS

  • "Silicon IP for Programmable Baseband Processing" by Eric Tell, Anders Nilsson & Christer Svensson from Coresonic

  • "1Tb/s 3W Inductive-Coupling Transceiver IP for 3D-Stacked SiP" by Noriyuki Miura from Keio University, Yoshihiro Nakagawa, Masamoto Tago & Muneo Fukaishi from NEC Corporation & Tadahiro Kuroda from Keio University Best IP Prize Candidate

  • "Hardware Implementation of a Combined Interleaver and DeInterleaver" by Shyam Shenoy, Chandrashekar B U & Sayandeep Nag from Synopsys (I) Pvt Ltd Best IP Prize Candidate

  • "IP CORE FOR RAID 6 HARDWARE ACCELERATION" by Michael Gilroy from Institute for System Level Integration & James Irvine from University of Strathclyde & Gideon Riddell from A2E Limited Best IP Prize Candidate

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