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"SoC Design Platform" Session

Moderated by Bart De Loore, NXP Semiconductors
Dec. 6, 2006 - 11:00-12:30
  • "Soc interconnect performance verification based on hardware emulator" by Denis LEHONGRE from STmicroelectronics

  • "A platform-based technology for fault-robust SoC design" by Stefano Lorenzini from YOGITECH SpA

  • "How a retargetable tool flow for ASIP design enables SoCs for multitudes of applications" by Gert Goossens, Dirk Lanneer, Werner Geurts & Johan Van Praet from Target Compiler Technologies

  • "A Platform Based SOC Design Environment" by Jeonghun Kim from Korea Univ/Mewtel Inc