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DAY 1: Tuesday November 30, 2010
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7:00 - 8:45
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Breakfast
and Registration
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AUDITORIUM |
| 9:00 - 9:30 |
Welcome: Welcome: An IP community: what for ? Impact of the evolution of the IP market
By Gabriele Saucier
CEO
Design And Reuse
An IP community :what for ? Impact of the evolution of the IP market
By Gabriele Saucier, CEO, Design And Reuse
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| 9:30 - 10:00 |
Keynote Talk: Keynote Talk: Semiconductor IP Market Overview, 2009-2014
 By Ganesh Ramamoorthy
Principal Research Analyst
Gartner
Semiconductor IP Market Overview, 2009-2014
By Ganesh Ramamoorthy, Principal Research Analyst, Gartner
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| 10:00 - 10:30 |
Keynote Talk: Keynote Talk: IP Challenges and Opportunities in China
 By Mark Ma
MBA, Founder
Jiatao Industrial
IP Challenges and Opportunities in China
By Mark Ma, MBA, Founder, Jiatao Industrial
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| 10:30 - 11:00 |
Break
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| 11:00 - 11:30
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Keynote Talk: Keynote Talk: Mobile Everywhere - How enriched mobile media is changing the IP landscape
 By Kent Shimasaki
Managing Director
Infinitedge
Mobile Everywhere - How enriched mobile media is changing the IP landscape
By Kent Shimasaki, Managing Director, Infinitedge
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| 11:30 - 12:00 |
Keynote Talk: Keynote Talk: Forecast 2011: Trends and Opportunities in the Embedded Market
 By Colin Walls
Mentor
Forecast 2011: Trends and Opportunities in the Embedded Market
By Colin Walls, Mentor
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| 12:00 - 12:30 |
Keynote Talk: Keynote Talk: Prototyping for Embedded Software Development
 By Frank Schirrmeister
Director, Product Marketing, System-Level Solutions
Synopsys
Prototyping for Embedded Software Development
By Frank Schirrmeister, Director, Product Marketing, System-Level Solutions , Synopsys
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| 12:30 - 13:30
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Lunch |
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AUDITORIUM |
KILIMANDJARO
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MONT
BLANC
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MAKALU
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| 13:30 - 15:00 |
Panel: Portability of Analog IPs in 32nm and beyond?Panel: Portability of Analog IPs in 32nm and beyond?
Moderator:
 Andreia Cathelin
Senior Design Expert
STMicroelectronics
Panelists:
- Pierre Dautriche, STMicroelectronics
- Christophe Bernard, STEricsson
- Dominique Henoff, STMicroelectronics
- Navraj Nandra, Synopsys
- Thierry Dumaure, Cadence
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Session: Design (1)Session: Design (1)
Chairman: Jean Francois Pollet (Dolphin Integration)
-"Is there a “one-size fits all” SOC PLL?" by Jeff Galloway, Randy Caplan (Silicon Creations)
-"Systematic approach to verification of a mixed signal IP. HSIC PHY case study" by Dariusz Pieńkowski, Dariusz Kaczmarczyk, Tomasz Klimek (Evatronix SA), Harry Peterson (Mohagi), Wojciech Sakowski (Silesian University of Technology),
-"Distributed Video Coding (DVC): Challenges in Implementation and Practical Usage" by Kodavalla Vijay Kumar (Wipro Technologies), P.G. Krishna Mohan (JNTU College of Engineering, Hyderabad)
-"The Challenges and Benefits of Raising Analog/Mixed-Signal Verification Above the Transistor Level" by Andy Betts, Daniel Saias (Asygn)
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Session: Design Methodology (1)Session: Design Methodology (1)
Chairman: Frank Schirrmeister, Director, Product Marketing, System-Level Solutions (Synopsys, Inc.)
-"TLM 2.0 Standard into Action: Designing Efficient Processor Simulators" by Luca Fossati (European Space Agency)
-"A UML REPRESENTATION OF A PASSIVE STANDBY POWER MANAGEMENT ARCHITECTURE FOR SET-TOP BOXES" by Robert Deaves, Alan Loyd, Elisa Vermaat-Cuoco, Nico Vermaat (STMicroelectronics)
-"STAC: Advanced inter-die communication Technology" by Andrew Jones, Stuart Ryan (STMicroelectronics)
-"Securing the integration of high-resolution ViCs on SoCs and SoCs on PCB " by Frederic Renoux (Dolphin Integration)
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Seminar: Seminar on VerificationSeminar: Seminar on Verification
Organizer:
 Fabian Delguste
Principal CAE
Synopsys
Seminar: Metric Driven Verification IPs Seminar: Metric Driven Verification IPs
Organizer:
 Gabriele Zarri
Verification IP Solutions Architect
Cadence
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| 15:00 - 15:30 |
Break |
| 15:30 - 16:00 |
Panel: Critical Success Factors for Platform-enabling IPPanel: Critical Success Factors for Platform-enabling IP
Moderator:
 Jack Browne
Sonics
Sr. VP of Sales and Marketing
Panelists:
- Marcello Coppola, R&D Director, STMicroelectronics
- Rick Tomihiro, Dir. of Marketing, Semiconductor IP, Xilinx
- Phil Dworsky, Director, strategic alliances & Publisher, Synopsys Press, Synopsys
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Session: Design (2)Session: Design (2)
Chairman: Paolo Pezzati (Cadence)
-"Advanced Power Management in Embedded Memory Subsystems" by Lisa Minwell (Synopsys)
-"USB3.0 application building using low performance 8-bit microcontroller" by Michal Jedrak (EVATRONIX SA)
-"icyflex: an ultra low power DSP core for portable applications" by Marc Morgan, Simon Gray (CSEM)
-"SPVR: An IP core for Real-Time Speaker Verification" by Joseana Fechine, Lucas Paixão, Adalberto Júnior, Fabrício Melo, Sérgio Espinola (UFCG)
-"Distributed Video Coding: Adaptive Video Splitter" by Kodavalla Vijay Kumar (Wipro Technologies), P.G. Krishna Mohan (JNTU College of Engineering, Hyderabad)
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Session: Design Methodology (2)Session: Design Methodology (2)
Chairman: Pierre Bricaud (Synopsys)
-"Automating Design Rule Waivers in SoC IP Reuse" by Sandeep Koranne, Anant Adke (Mentor Graphics Corporation)
-"An IP-XACT Deployment Case: IZARN IP" by Ates Berna (ST-Ericsson), Sparsh Arun (STMicroelectronics), Seyda Aygin, Sinan Topcu, Emrah Armagan (ST-Ericsson)
-"Integration-Optimized IP from Cadence" by Ranga Srinivasan, Brian Gardner (Cadence)
-"Optimizing System Management in the Platform SoC Era" by Howard Pakosh (ChipStart)
-"Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Multi-FPGA" by Khawla HAMWI (ENSTA ParisTech), Omar HAMMAMI (ENSTA ParisTech)
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Break
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| 16:00 - 17:00 |
Session: Verification / ValidationSession: Verification / Validation
Chairman: Helena Krupnova (STMicroelectronics)
-"Improving Verification Efficiency Using Application Specific Instruction Processors" by Frank Schirrmeister, Achim Nohl, Drew Taussig (Synopsys)
-"Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster" by Kesava Talupuru (MIPS Technologies Inc.)
-"Guidelines for successful SoC Verification in OVM/UVM" by Moataz El Metwally (Mentor Graphics)
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| 17:00 - 17:15
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Break
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| 17:15 - 18:45
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Session: Test &DebugSession: Test &Debug
Chairman: Helena Krupnova (STMicroelectronics)
-"Guidelines for SystemC – Debugger Integration" by Mohit Paul (NXP Semiconductors)
-"ATPG Tool Migration" by Pitchumani Guruswamy, Venkateshwaran Natarajan
-"SerDes in High Reliability, Long Reach Applications" by Claude Gauthier (MoSys)
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Panel: IP and SoC verification what's key to day ? a good verification plan, verification flows, verification services, Verification IPs or all of that?Panel: IP and SoC verification what's key to day ? a good verification plan, verification flows, verification services, Verification IPs or all of that?
Moderator:
 Laurent Ducousso
STMicroelectronics
Panelists:
- Huy-Nam Nguyen , BULL
- Thomas Goust , IP and SOC Verification Team Leader, ST Ericsson
- Gabriele Zarri, Verification IP Solutions Architect , Cadence
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| 19:00 - 21:30
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join the French Café and enjoy regional food, French wine and songs
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DAY 2: Wednesday December 1, 2010
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7:00 - 8:45
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Breakfast
and Registration |
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AUDITORIUM |
MAKALU
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| 8:45 - 9:00 |
Welcome
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Session: Exhibitor TrackSession: Exhibitor Track
Chairman: Hein van Der Wildt
-"VIRTUAL PROTOTYPING – Enabling the SW development Eco-System around new semiconductor platforms" by Pierre Bricaud (Synopsys)
-"Cadence Incisive Verification IP" by Gabriele Zarri (Cadence)
-"Large FPGA boards for ASIC prototyping" by Mike Dini (DINI Group)
-"Battling the On-chip Memory Bandwidth Bottleneck" by Jack Browne (Sonics)
-"FPGA-based High Performance Computing" by Mike Dini (DINI Group)
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| 9:00 - 9:30 |
Invited Talk: Invited Talk: IP Acquisition & Management
 By Kurt Wolf
Founder and President
SiliconIP
IP Acquisition & Management
By Kurt Wolf, Founder and President, SiliconIP
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9:30 - 10:00
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Invited Talk: Invited Talk: Intranet IP Management: Status and Challenges today
By Gabriele Saucier
Design And Reuse
Intranet IP Management: Status and Challenges today
By Gabriele Saucier, Design And Reuse
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| 10:00 - 10:30
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Break |
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AUDITORIUM |
KILIMANDJARO
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MONT
BLANC
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MAKALU |
| 10:30 - 11:00 |
Invited Talk: Invited Talk: Plug-And-Play IP for FPGA Based SoC Design
 By Rick Tomihiro
Xilinx
Plug-And-Play IP for FPGA Based SoC Design
By Rick Tomihiro, Xilinx
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Invited Talk: Invited Talk: Post- Silicon Debug: A New Approach for Solving the Unspoken and the Urgent
 By Kathryn Kranen
Jasper
Post- Silicon Debug: A New Approach for Solving the Unspoken and the Urgent
By Kathryn Kranen, Jasper
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Invited Talk: Invited Talk: High Speed Interfaces, cases study of IP solutions: USB 3.0 and MIPI
 By Dr Eric Esteve
IPnest
High Speed Interfaces, cases study of IP solutions: USB 3.0 and MIPI
By Dr Eric Esteve, IPnest
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Invited Talk: Invited Talk: Patenting the Intellectual Properties
 By Yvon Gris
Cabinet Gris
Patenting the Intellectual Properties
By Yvon Gris, Cabinet Gris
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| 11:00 - 11:30
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Invited Talk: Invited Talk: Delivering complete solutions on an FPGA
 By Bob Blake
Product and Corporate Marketing Manager
Altera Europe
Delivering complete solutions on an FPGA
By Bob Blake, Product and Corporate Marketing Manager, Altera Europe
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Session: Quality & VerificationSession: Quality & Verification
Chairman: Kathryn Kranen (Jasper )
-"Quality Maturity Server (QMS) - Case Study" by David Ling (Freescale Semiconductor Inc.)
-"Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP" by Pankaj Singh (Infineon Technologies), Gaurav Kumar Verma (Mentor Graphics)
-"Software Driven Verification" by Achim Nohl, Frank Schirrmeister (Synopsys)
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Session: Embedded SystemsSession: Embedded Systems
-"xLuna: a Real-Time, Dependable Kernel for Embedded Systems" by Giovanni Beltrame (Ecole Polytechnique de Montreal), Luca Fossati, Marco Zulianello (European Space Agency), Pedro Braga, Luis Henriques (Critical Software)
-"Embedded System realization with Multi-objective SOC Architecture for Vehicular Systems" by Sesha Giri Rao M (Department of Information Technology)
-"Engineering-SaaS CAD System for Embedded System Design, FlowrianII" by Ming MA (System Centroid Inc.), Hyung Kie YUN, Woo Kyung LEE, JungSeop SEO (Hoseo University), Inhag PARK (System Centroid Inc.)
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Seminar: How to optimize Data-flows in a Multicore SoC Seminar: How to optimize Data-flows in a Multicore SoC
Organizer:
 Eric Bost
Senior FAE High End processors
Freescale Semiconductors
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| 11:30 - 12:00 |
Invited Talk: Invited Talk: Porting High-Performance IP to Low-Cost, Mid-Range FPGA
 By Tim Schnettler
Director, Product Marketing
Lattice Semiconductor Corp.
Porting High-Performance IP to Low-Cost, Mid-Range FPGA
By Tim Schnettler, Director, Product Marketing, Lattice Semiconductor Corp.
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| 12:00 - 12:30 |
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| 12:30 - 13:30 |
Lunch
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AUDITORIUM
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KILIMANDJARO
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MONT
BLANC
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MAKALU |
| 13:30 - 15:00
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Panel: IPs on FPGA :Strategy and Vision Panel: IPs on FPGA :Strategy and Vision
Panelists:
- Bob Blake, Product and Corporate Marketing Manager, Altera Europe
- Rick Tomihiro, Xilinx
- Tim Schnettler, Director, Product Marketing, Lattice Semiconductor Corp.
- Hal Barbour, President , CAST
- Eric Esteve, IPnest
- Kurt Shuler, Director of Marketing , Arteris
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Session: Multi processor &NoCSession: Multi processor &NoC
Chairman: Antonio-Marcello COPPOLA (STMicroelectronics)
-"Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices" by Mazen Khaddour, Omar HAMMAMI (ENSTA)
-"MultiFPGA Design Based 64 PE with NoC Extension" by Abir M'zah, Omar Hammami (ENSTA)
-"Virtual Channels Hardware Support In Switches in Relation to NoC Costs, Functions and Features" by Yuriy Sheynin, Elena Suvorova, Nadegda Matveeva, Artur Eganyan (Saint Peterburg University of Aerospace Instrumentation)
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Seminar: Safety-Security Critical SystemsSeminar: Safety-Security Critical Systems
Organizer:
 Huy-Nam Nguyen
BULL
Speaker:
- UPMC/Lip6
- Dominique Ragot, Thales
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