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Panel: Platform & Subsystem IP: Trends and Realities

Since the mid-1990s when the concept of reusable IP cores first came into being, the proposal has always been that it was more economical to use and reuse IP than to always design chips from a clean start. It was also faster to market and more resource efficient. Many 3rd party IP companies came into being to supply IP that could be considered standard or that was so complex to design that doing the same function over and over was simply not practical. An example of the former would be a function like an Ethernet MAC and the latter would be something like a processor. Over the years this has proven to be a very successful practice for both chip designers and IP vendors and is one of the cornerstones of today’s business.

In the last few years with the exponential growth in gates available from the silicon suppliers, the pressure to use those gates to provide much more advanced functionality on a per chip basis has grown more and more intense. Functionality that is common in today’s smart phones, for example, was out of reach only a few short years ago. Getting to market in only a few months at price points that are astoundingly low is necessary for success. Many believe that this is the result of a shift to designing around reusable platforms and whole subsystems which gives entirely new meaning to the reusable IP concept. The idea of building a platform around which several different sets of functionality could be brought to market was viewed as something only the largest companies could engineer. Lately, there has been much hype about the 3rd party vendors expanding their offerings to at least the subsystem, if not the platform, level. The idea is to bring to the general market the advantages of higher levels of design reuse in effect recreating the success of IP cores at the next level. Is this really coming to pass or just industry hype and clever marketing? Do customers really want this and can the industry really deliver the kinds of flexibility customers will demand?

This panel attempts to examine the trend and discuss the realities of today’s platform IP market in addressing the requirements of both ASIC and FPGA designers.

Panelists:

		Bill Finch CAST
		Jack Browne Senior Vice President of Marketing Sonics
	Jack Browne is Sonics’ Senior Vice President of Marketing. Prior to joining Sonics, Mr. Browne served in several executive roles at MIPS Technologies, including executive vice president of worldwide sales and executive vice president of marketing. Earlier in his career, he was the head of Motorola’s 68000 processor marketing team. An acknowledged industry spokesman, Mr. Browne has written more than 100 papers for industry publications and presented at more than 100 industry conferences. He holds a B.S.E.E. degree from the University of Texas.
		Eric Esteve IP Nest
	Eric has over 25 years of experience in the Semiconductor industry, focused on ASIC and IP. He is the founder of IPnest, a company which provides strategic consulting and IP related Market Surveys to high level customers, IP vendors, Chipmakers and Foundries. Eric is also one of the four founding bloggers working with the Semiconductor Wiki Project, the premier semiconductor collaboration site, a growing online community of professionals involved with the semiconductor design and manufacturing ecosystem.
		Peter Hirt Director IP Sourcing STMicroelectronics
		Martin Lund Senior Vice President, Research and Development, SoC Realization Group Cadence
	Martin Lund is senior vice president of research and development for the SoC Realization Group. His primary focus is to expand the Cadence design IP portfolio, enabling customers to realize their System-on-Chip (SoC) products faster, cheaper, and with higher quality. This is a strategic growth area for Cadence that includes all digital and analog IP development and design services engagements. Prior to joining Cadence, Lund spent 12 years at Broadcom, most recently as senior vice president and general manager of Broadcom's Network Switching Business. Under his vision and leadership, Broadcom became the undisputed global leader in Ethernet switch silicon for data center, service provider, enterprise, and SMB markets. Before Broadcom, Lund held various marketing and senior engineering management positions at Intel Corporation and Case Technology. Lund is an inventor on 26 issued and pending US patents. He holds a technical degree from Frederiksberg Technical College and Risø National Laboratory at the Technical University of Denmark.