Faster and safer design for integration of power-optimized SoCs
New generations of battery-powered consumer and industrial devices often rely on more complex architectures, but this comes at the cost of increased power consumption. Thus, SoC Integrators will face exponential power dissipation if they do not change their traditional design approach.
The most efficient solution to reduce power consumption is to partition the SoC in power and voltage islets with several states of activity.
The challenge for SoC Integrators is to adapt their existing integration flow with the hierachy to reach the lowest power consumption without impacting the robustness of the device.
This seminar organized by Dolphin Integration introduces a methodology for designing and integrating safely power-optimized SoCs, guiding SoC integrators and Fabless suppliers at all steps of the integration flow, from the selection of the appropriate power management architecture to the final sign-off checks.
CTO for analog developments
|First Session: How to define a robust and power-optimized power management architecture|
One of the two major issues faced by SoC Integrators and Fabless suppliers when implementing power islets in a SoC is to properly select the power management network (PMNet) including power regulators, external capacitors and internal capacitors to sustain the voltage drop caused by mode transitions. If the PMNet is undersized, the SoC may not operate properly. On the contrary, if the PMNet is over-designed, silicon area will be wasted or the Bill-of-Material will be more expensive than necessary.
This first part of the seminar will cover the following topics:
Sébastien Genevey received the Master’s Degree in Integrated Circuit design from the Polytechnical Institute of Montpellier, France. He enters to Dolphin in 1997 as analog designer for mixed-signal products. He is currently CTO for analog developments for audio, metrology and power management products.
- The role of PMNet in power-optimized SoCs
- What are the different kind of power regulators and their relative benefits
- What is the Interface Distributing Power and how to define it
- Demonstration on a case study of the methodology to define the best PMNet architecture depending on user challenges (area, BoM cost, consumption...)
Development Manager for the SoC Integration Product Line
|Second Session: How to detect and fix design issues due to mode transitions all along the integration flow|
This second part of this Dolphin seminar will present a complete methodology for limiting the impact of mode transitions on the functionality of the SoC, but also on Time to Tape Out and on performances.
This second part of the seminar will address the following topics:
Lucille Engels received the M.S. degree in Electrical Engineering from the Polytechnical National Institute of Grenoble, France, in 1999. In 1999, she joined Dolphin Integration, Meylan, France, working in logic design for mixed-signal CODECs and in mixed-signal SoC integration. As development manager for the SoC Integration Product Line, she has been involved concretely in the innovative concepts and practices needed to enable mixed-signal and low-power SoC/ASICs in multi domain systems: starting with early floorplanning to solve power consumption and noise issues, mastering multi-level equivalence checks between models, completed with the virtual fabrication process and the virtual test.
- The central role of simulation with behavioral models at each step of the integration flow
- The issue of islet construction: what is the best islet implementation style, how to size the power switches and how to manage the power-up sequence will be some of the questions raised here.
- Application on a 55 nm design of the complete methodology for faster and safer design and integration of power-optimized SoCs