32-bit RISC processor: Configurable, small size, embedded performance

Ultra-Low Latency H.264 Video Encoding Now Available from CAST
sureCore receives GBP250K SMART Award to prototype its low power SRAM technology
Automated ECO Flow for overall cycle time reduction
SoC Interconnect Verification Challenge
The Power of Developing Hardware and Software in Parallel
Industry's First Demo of USB 3.0 SSIC and MIPI M-PHY Passing USB Compliance Tests
How much of the chip does IP fill
Where Have All the IP Vendors Gone? Part 1
DAC Village
June 2-6, 2013
|
DAC Village >> June 2-6, 2013 |
Shanghai Event >> September 4, 2013 |
Beijing Event >> September 12, 2013 |
Grenoble Conference >> Nov. 6-7, 2013 |
Introduction :IP Market Demands and Offers
By Gabriele Saucier
President and Chief Executive Officer
Design And Reuse
Biography:
Gabriele Saucier received her PhD from the University of Grenoble, where she was a professor and headed a research lab on Integrated System Design. She has published more than 350 papers in the design and EDA fields. Dr. Saucier is an IEEE fellow for her contributions in synthesis, test generation and fault tolerance. Leaving her university career, in the 1990s she founded a synthesis company, IST (Innovative Synthesis Technologies), mainly dedicated to FPGA synthesis, and in 1997 Design and Reuse, dedicated to IP-based design. She has launched two successful conferences - Euroasic and IP/SoC.
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