Agilent Technologies Uses Zenasis Technologies' ZenTime to Increase System-on-Chip Performance and Accelerate Time to Silicon

"ZenTime is a unique EDA tool that helped us improve SOC performance to meet our design objectives," said Jay McDougal, IP design methodology program manager for Agilent's Imaging Solutions Division. "With ZenTime, we saw significant timing improvement on one of our most challenging IP cores. Using ZenTime helps Agilent maintain its SOC integration and performance leadership."

The Agilent SOC created with ZenTime operates at 400 MHz, has 134 input/output signals and uses two million logic gates. The SOC includes the ChipWrights CWv16 DSP core, a 2.5 V PLL, DMA, AMBA AHB bus bridge, as well as bus monitor and arbiter. With this SOC, Agilent extends its SOC leadership into the 90-nm generation.

"It's gratifying to help companies like Agilent meet their design performance targets on time, and often ahead of schedule," said Jay Roy, CEO and co-founder of Zenasis Technologies. "The combination of ZenTime and ZenCell Factory has been successfully used to improve benchmarked design performance by 10 percent or more after using today's best available optimization tools and methodologies."

About Agilent's ASIC Solutions

With three decades of ASIC design and manufacturing experience, Agilent offers state-of-the-art hierarchical design methodology and design-for-test capability. The company has a consistent record of first-pass success in the design and manufacture of these chips, and provides in-depth system-level design experience, assurance of supply, and total life-cycle support. These strengths, combined with an extensive IP portfolio, facilitate rapid integration of quality, high-performance ASICs for applications, including communications, imaging, storage and computing. More information is available at www.agilent.com/view/asic.

About ZenTime

ZenTime is a standard cell-based timing optimization tool able to achieve timing closure for existing nanometer designs that have already been through logic optimization and physical synthesis. ZenTime uses a unique hybrid of logic, physical and transistor-level optimization to help ASIC and SOC design teams improve their performance by 10 percent or more. ZenTime automates the process of generating design-specific cells on the fly, and provides cell-based designers with the benefits typically found in the custom design methodologies while retaining the time to silicon benefit of automated standard cell-based design flows.

About Agilent Technologies

Agilent Technologies Inc. is a global technology leader in communications, electronics, life sciences and chemical analysis. The company's 28,000 employees serve customers in more than 110 countries. Agilent had net revenue of $7.2 billion in fiscal year 2004. Information about Agilent is available on the Web at http://www.agilent.com/.

About Zenasis Technologies

Zenasis Technologies, Inc. provides next-generation design optimization tools for standard cell-based design, which help bridge the gap between ASIC and custom IC designs. Zenasis' suite of tools consists of ZenTime, a timing optimization tool, and ZenCell Factory, an automatic standard cell creation tool. Its context-specific "hybrid optimization technology" operates at the gate, physical and transistor levels for a given design placement, and empowers designers to improve performance, power, area and routing. Zenasis helps cell-based designers meet the demands for higher performance; faster timing closure and cost-reduction without changing their existing process technology or design flows. Corporate headquarters is located at 1671 Dell Ave., Suite 100, Campbell, CA, 95008. For more information, please visit the company's Web site at http://www.zenasis.com/.

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