A matter of the design chain
EE Times: A matter of the design chain | |
Mark Templeton (04/18/2005 9:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=160901315 | |
Four critical technologies must come together for the success of a chip design: commercial intellectual property; electronic design automation tools and flows; foundry process information; and the design team's own custom design and chip assembly technique. Let's look at each in turn.
Most commercial IP is high-integrity and low-risk. It has usually been proven in silicon on tens, hundreds or possibly thousands of designs across a large number of processes. A similar argument can be made for commercial design tools. The user community for leading EDA tools is huge. By and large, EDA tool quality is outstanding. Occasionally, a design may fail because a simulation or verification step was not performed thoroughly, but rarely is a tool to blame.
The third critical piece of the puzzle is the foundry's own process models, DRC flows, etc. Even the smallest issue with this level of process abstraction can lead to poor results. Most foundries have become expert at establishing and exhaustively testing these models. Still, it is common for a new process to undergo a transition once volume experience is gained from early customer designs.
The circuitry newly created by the designers will rely totally on the accuracy of the process information, the analysis of the design tools and the skill of the design team. This is where the opportunity is and where the strong design chain partnerships that exist among the foundry, EDA vendors, IP vendors, flow developers and, of course, the actual chip design team come into play.
By Mark Templeton, president and chief executive officer of Artisan Components Inc.
| |
- - | |
Related News
- Atmosic Introduces the Multiprotocol ATM34/e Series Adding 802.15.4 Support for Thread and Matter to its Bluetooth LE Portfolio
- Apple-TSMC-Amkor Pact Bolsters U.S. Chip Supply Chain
- proteanTecs Collaborates with BAE Systems to Enable a Zero Trust Supply Chain for Defense Applications
- ShortLink AB joins X-FAB's Design & Supply Chain Partner Network and IP Portal
- Supply Chain Experts Weigh In on CHIPS Act
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |