VSIA readies Web tool, system-level design specs

VSIA readies Web tool, system-level design specs
By Rick Merritt, EE Times
December 11, 2000 (5:48 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001211S0065

MANHASSET, N.Y. — In an effort to boost adoption rates for its system-chip standards, the Virtual Socket Interface Alliance is developing a Web-based tool to help verify a core's compliance to its specifications. The group is also queuing up the release of a number of new specs, including some of the first deliverables from its system-level design group, by the end of the year.

Within six months the VSIA hopes to have the latest version of its Deliverables Document, version 2.3 released in late October, in the form of an Internet-based checklist to validate whether a given component complies with the group's specs. "We're trying to make the standards even easier to use," said Timothy O'Donnell, president of the VSI Alliance.

Getting broader adoption of the specs the group has been hammering out since 1997 is one of the key goals of O'Donnell, who took the president's spot in June. "The adoption hasn't been as fast as we had hoped, and sometimes we are not getting 100 percent adoption, but people are using our specs as the basis for their own work. But the good news is adoption is happening," he said.

Meanwhile the group continues to crank out work, estimating it will have released a total of 19 specifications by the end of this year. Three new standards — in the areas of verification taxonomy, cataloging attributes for virtual component transfers and an advanced on-chip bus interface — are going through a final editing stage now and are set for release before the end of the year.

In addition, the system-level design group of the VSIA is expected to roll out its first deliverables in the next few weeks. The first of those efforts is a system-level interfaces spec (SLIF), which draws a line between the functional part of a core and its interface. The other piece is a data-type model expected in the first quarter of next year, which will enumerate standard data types in a system-level design la nguage.

The latter effort is important because multiple system-design languages are now emerging in the market and system-chip makers need a way to import and export information across the various environments. "It doesn't seem like there will be any convergence in these tools for some time," said O'Donnell. The data model "is far enough along that some people are starting to study using it in areas like the SystemC environment," he added.

"We've done a lot of work on the area of RTL to silicon, but now we need to turn to the higher-level issues in system design. A lot of our future is in this system-level design area, but it is still pretty nebulous," O'Donnell said. "I'm not sure how quickly we will be able to get to deliverables here."