Structured ASICs not just for small chip players

As it turns out, they're not just for the little guys. In some cases, big chip companies are giving in to temptation and choosing structured ASICs as a way to get a chip out the door quickly or to deal with tight R&D budgets.

Altera Corp. announced last week that Texas Instruments Inc. had used its HardCopy structured ASIC for a Digital Light Processor chip set. The announcement with TI comes a few months after Infineon Technologies AG announced it had developed an Ethernet-over-Sonet device using HardCopy.

Why would either of those companies hire someone else to do the work, when each has its own army of chip designers? According to Altera, there's a given minimum amount of time required to design, debug and prototype an ASIC using conventional design practices. Say a chip company wants to have something to show off at the next trade show but is running behind schedule. A structured ASIC could be the way out of the jam.

In TI's case, Altera was able to deliver the first HardCopy samples 10 weeks after the design was finalized, according to the supplier.

"Standard ASIC development takes two years, and it doesn't matter how many resources you put into it. At some point, you can't compress the design cycle" further, said Alain Bismuth, vice president of Altera's HardCopy product group. "I was meeting with another large semiconductor company a few days ago, and they were telling me exactly the same thing."

Structured ASICs are not as dense or as fast as standard-cell devices, but they are faster and denser than FPGAs, and they take less time to prototype than standard-cell chips. For some companies — and some projects — that's reason enough to develop a chip that's good enough.

Other structured-ASIC vendors also report high interest among semiconductor companies. Since it introduced its first structured-ASIC platform about a year ago, Faraday Technology Corp. has brought about 10 companies on board. Two-thirds of them are chip companies, said Charlie Chen, vice president of international business at Faraday (Sunnyvale, Calif.).

Many companies, Chen said, consider the cost of developing a 0.13-micron chip prohibitive in many cases. "Unless you have a million units a year," he said, "it probably doesn't make very much sense."

Cell blocks
In Faraday's case, 60 percent of the chip is filled in with standard-cell gates before it is received by the customer. The pre-engineered portions include such blocks as control logic for standards like Ethernet or DDR memory.

It's hard to tell whether chip companies will move to structured ASICs in droves. Structured-ASIC vendors are usually barred from disclosing customers, so when Altera got permission to use the names of some high-profile chip houses, the company understandably tried to make the most of it.

That Altera's No. 1 competitor, Xilinx Inc., continues to pooh-pooh structured ASICs gives Altera even more reason to fan the publicity flames. At the very least, the customer announcements may give the uninitiated a reason to take a look.