SANTA CLARA, Calif. A fabless ASIC shop ready to open for business may be the wave of the future provided it can deliver what it promises. Run by Cadence veteran Jack Harding, eSilicon Corp. has positioned itself as an "ASIC general contractor" and says it will deliver foundry access to its customers.
The startup so new that its corporate Web site is slated to come up Monday (Dec. 4) will offer system companies, large semiconductor makers and fabless design companies a range of design and manufacturing services, from feasibility planning to packaged chips.
"We are a horizontally integrated, fabless ASIC company," said Harding, its president and chief executive officer. "We're taking a general-contractor role, and customers don't have to speak to anyone else." Harding held the same positions at Cadence Design Systems during a turbulent time in that company's history.
Already, eSilicon has alliances with three intellectual-property (IP) providers, a packaging and test services supplier, and two foundries. The startup also announced its first customer, Antara.net (Santa Clara, Calif.), a provider of Internet testing products.
The company, which has around 60 employees, was launched with a $9 million investment from Crosspoint Venture Capital and is currently closing its second round of funding. "We've already engaged six or seven customers, and we don't even have a sign up out front," Harding said.
The cofounder and current executive vice president of eSilicon is Anjan Sen, who formerly was president of PulseCore Semiconductor. Keith Lobo, chief operating officer of Chips and Technologies Inc. and former CEO of Quickturn Design Systems, is on the board of directors.
While the startup will leverage the Internet for communications, it will earn revenues from the delivery of packaged and tested chips.
Don't take the "e" in eSilicon too literally, said Harding. "There's nothing dot-com about us. We just use the Internet as a convenient tool to pass data around the world."
While eSilicon plans to serve a wide range of customers, one of its major strengths will be its ability to secure foundry capacity for small customers, Harding said. The company will also provide services in physical design, packaging and test, and offer an infrastructure that many potential customers lack.
Less than leading-edge
But eSilicon is not for designers of leading-edge ICs. The company currently serves 0.18-micron design only, and it works with chips of under 4 million gates and less than 150 MHz. But that "mainstream" market is plenty big, with around $12 billion in annual revenues today, Harding said.
There are two ways to do business with eSilicon. Customers can provide a gate-level netlist and have eSilicon do the physical design, or they can hand over a GDSII layout file and have eSilicon contract with a foundry and deliver packaged chips.
The company also off ers IC Advisor, an online design-planning tool that can give estimates of die size and performance. It's an OEM version of Aristo Technology's IC Wizard product. Harding said eSilicon will gradually work toward silicon signoff at that high architectural level, starting with RTL signoff in 2002.
Bryan Lewis, chief semiconductor analyst at Dataquest Inc., believes eSilicon's plans are on target. "I think fabless ASIC suppliers will be the wave of the future," he said. "By not having a fab, you have more money to invest in value-added libraries and system knowledge."
Lewis said that eSilicon will have a lot more clout with foundries than small companies and will be more likely to get foundry access. "Foundries are being maxed out in terms of the total number of customers they can deal with," said Lewis. "And they [eSilicon] can guarantee the final chip, something foundries have been very reluctant to do."
But the fledgling company also faces several challenges, cautioned Lewis. One is finding enough design talent. Another is guaranteeing fab capacity, which is tough for companies of any size.
The two foundries that have signed on as eSilicon partners are Taiwan Semiconductor Manufacturing Co. (TSMC) and Silterra Malaysia.
"We believe that eSilicon's model is what many of our customers need to accelerate the process of getting their chips to market," said Mike Pawlik, vice president of corporate marketing at TSMC.
Harding said he has secured some capacity commitments from TSMC but wouldn't go into any details about exactly how many wafers.
The company has partnered with Palmchip for platform-based IP, inSilicon for communications-based IP, and Artisan Components for IC libraries and memories.
Packaging and test services will be offered through a partnership with Amkor Technology. Software for design flow, and tool logistics comes from Runtime Design Automation.
Antara.net is bringing a 2.5-million gate "Web stressing" chip to eSilicon for physi cal design and fabrication, said Huzefa Cutlerywala, hardware design manager at Antara.net. "The most important reason is that they were able to offer us wafers through TSMC," Cutlerywala said.
Secondly, he noted, eSilicon is providing packaging, testing and production services. "I would have had to set up my own team with my own test engineers to get an established flow going," Cutlerywala said. "I'm getting all that from eSilicon, albeit with a premium on price."
That premium, Cutlerywala said, is around 20 to 30 percent. But he believes it's worth it for his company, which does two or three chip designs per year. "For small customers where the volume is not high, there's a fair likelihood we may not get a continuous stream of wafers," he said.
Harding said that eSilicon is expecting to receive a netlist from Antara.net in April, will tape out by September, and deliver the chips by the end of the year. That may not sound fast, he said, but right now eSilicon is looking to refine its process wit h a small number of selected customers who are not in a hurry. Within a year, Harding said, eSilicon should be able to slash ASIC time-to-market by 25 percent and eliminate a lot of rework.
Not owning a fab is an important part of the company's business model. "If you're a leading-edge ASIC supplier you own a fab, and profitability is only through high-volume production," Harding said. "We don't have that burden. We can take smaller customers and give them excellent high-touch service."
That service starts with IC Advisor, which Harding believes will give ASIC designers "an enormous time-to-market advantage." That's because the initial stages of chip planning and feasibility typically take four to 12 weeks, he said.
By February, a full version of IC Advisor will be available without charge at the company's Web site. But paying customers "will have access to more and better information," Harding said.
Dave Reed, vice president of marketing at Aristo, noted that IC Advisor is essentially Aristo 's IC Wizard block-based planner with some added functions for die size estimation and package selection. "They put together a Web-based interface where people can pick up IP blocks, build a rudimentary netlist, and pass it off to [IC Wizard]," said Reed. "They parse our report files and generate other useful information they want to pass to their customers."
For those customers who hand off a gate-level netlist, eSilicon will take care of all physical design functions, either with its in-house staff or through partnerships. The company has about a dozen layout designers today, and does not expect to have a huge staff. "I don't want 300 engineers designing on my payroll," said Harding, who oversaw a large design services operation at Cadence. "It's an unproven model."
Instead, Harding said eSilicon, as it grows, will use the Web to establish a network of contract designers, using the Net to create a virtual company that can expand and contract with the business. "Our goal is to have access to hundreds of designers all over the world," Harding said.
Customers who hand off a GDSII file can use eSilicon's "smart COT [customer owned tooling]" services in which eSilicon handles product engineering, design-for-test and yield analysis, as well as taking responsibility for delivering tested chips. A significant feature is status-checking software that allows users to view what's happening with their chip at each step of the way.
Harding said eSilicon is working with several unnamed "world-class" integrated device manufacturers (IDMs) to license silicon intellectual property for 0.18-micron designs. While these IDMs themselves are moving to 0.13 microns, many of their customers are happy with 0.18 microns, and eSilicon hopes to secure their business.
Indeed, Harding said he has been surprised by the fact that large IDMs, looking to outsource more of their manufacturing, have been among the first companies to show interest in working with eSilicon. "They will sit back and say, 'at the end of the day, we don't want to build a thing,' " Harding said.
If a chip doesn't work, Harding said, eSilicon takes responsibility. "You can only charge for value add if the buck stops at your door," he noted.
Harding expressed confidence that eSilicon's revenue potential is hundreds of millions of dollars annually. The market eSilicon serves, he said, will grow to $25 billion within four years. Already, he noted, the new company is having to be very selective about customers it accepts, since demand far outstrips supply. "Initially, I am not looking for hundreds of customers, but a handful," he said.
"This industry is desperate for a new way of doing business," Harding said.
Rick Merritt contributed to this report.