English
Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
TransEDA announces Assertain, the first independent Verification Closure Management tool
Los Gatos, CA and Eastleigh, UK - May 30, 2005 - TransEDA, the leader in Coverage and Verification Measurement solutions for electronic designs, today announces the launch of AssertainTM, the first independent Verification Closure Management (VCM) tool that delivers, in a single environment, total measurement and control of the digital design verification process.
Covering all front-end design stages from original text specification through to validated RTL, Assertain(TM) monitors, measures and manages the verification process in one integrated environment. The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test grading and optimization, linked to specification coverage using proven requirements traceability techniques.
Verification Closure Management
Verification Closure is achieved when a pre-defined level of confidence in the correctness of a design has been attained. Such confidence comes when the design team can prove that all design requirements has been implemented and verified.
Increasing circuits complexity, time-to-market, corner-case bugs - and more - all conspire to compound the verification problem. Project managers are forced to make a trade off between the level of verification achieved, time-to-market, and the risk of taping out a non-functional chip.
To overcome these issues, engineering teams had to multiply their verification resources and augment the verification time in an attempt to decrease the risk of an expensive re-spin. The main reason for this inefficiency is the lack of unified and accurate measures of verification quality and completeness.
TransEDA enhances control of the verification process
AssertainTM has been built around a revolutionary assertion coverage technology. Deploying comprehensive and unique assertion coverage metrics such as structural, step and variable coverage, TransEDAs solution enables precise measurements of how well assertions have been exercised by simulation, and how well they cover the intended behavior.
The cross-linked results from assertion coverage and code coverage are combined in a single, unified database that provides a clear view of how design verification is progressing.
Seamless mix of static and dynamic technologies
In addition to recording code and assertion coverage from dynamic simulation, TransEDA has embedded in AssertainTM its customer-proven formal engine, to be used transparently where formal algorithms are best suited to address a verification problem.
This engine augments the capabilities of the tools integrated rule checking with advanced formal verification of design consistency rules, such as bus contention and high impedance, FSM deadlock and livelock, array out-of-bound, etc. Formal technology is also used to automatically check protocol coverage and compliance with bus standards such as OCP, AHB and AXI.
Empowered by Coverability Analysis, and linked to initial specifications
Assertions which are not fully coverable not only slow down simulation, but may also appear to pass only because they are not reachable, thus giving engineers a false sense of security and increasing the risk of an re-spin.
TransEDA has integrated its unequaled Coverability Analysis technology into AssertainTM. Design Coverability Analysis can shave weeks off the verification time by applying formal techniques to identify areas where additional testing should be directed, filtering out those that are not reachable.
Assertion Coverability Analysis similarly provides an accurate measure of the effectiveness of PSL or SystemVerilog Assertions in a design.
However, verifying that the product is being built right is useless if one does not ensure that the right product is being built. AssertainTM provides a unique solution linking specification requirements, RTL, assertions and tests, to give engineers the ability to automatically track and verify that all original design requirements have been met and properly tested, therefore providing, for the first time, a specification coverage metric closely linking the specification, the RTL and test-benches via assertions.
An open and independent solution
Independent of platforms, languages, EDA vendor or verification tools, AssertainTM provides a single data point for the Assertion-Based Verification (ABV) approach.
GUI or command line interfaces combined with interactive or batch mode operations enable the tool to easily fit into any existing design flow. TransEDA users enjoy full backwards compatibility with existing TransEDA tools and results files allowing a smooth and seamless up-grade path.
The Logical Step to Verification Closure
For long, users have had to use a collection of separate verification tools, such as simulation, emulation, acceleration, pseudo-random testbench generation and formal verification. However, despite the current trend to integrate these point tools in platforms, they are still not working smoothly together, mainly due to the lack of common metrics to measure what these technologies really verify.
AssertainTM, TransEDAs new generation product represents a major advance in delivering a coherent and integrated verification closure solution. The results from specification coverage, assertion coverage, advanced code coverage, and coverability analysis are combined in a single, unified set of metrics and cross-linked together to provide a complete audit of your design as you progress towards a successful and faster tape-out. TransEDA is the only company to offer an open and independent solution for Verification Closure Management.
Pricing and Availability
AssertainTM is available on Solaris and Linux. Pricing starts from $30K for a perpetual license.
TransEDA will demonstrate this innovative new approach to design verification at the 42nd DAC (Design Automation Conference) June 13 17, 2005, in San Diego, CA.
About TransEDA
TransEDA is a leading provider of coverage and verification measurement solutions for electronic designs.
The company develops an advanced Verification Closure Management environment that takes advantage of both static and dynamic technologies to give engineers access to a unified view of the design verification progresses.
Unique functionalities such as comprehensive assertion coverage, coverability analysis, specification coverage with engineering change impact analysis, and automatic bus protocol checking, enhance the traditional code coverage, test suite optimization, HDL rule checking and static assertion checking capabilities to form an integrated Verification Closure Management solution.
Other products include verification IP with bus-based system-level test automation and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, plus local representatives in China, India, Korea, Singapore and Taiwan.
For more information, visit www.transeda.com.
TransEDA, the TransEDA logo and Verification from Concept to Reality are registered trademarks of TransEDA Technology Ltd.
All other trademarks are the property of their respective owners.
Covering all front-end design stages from original text specification through to validated RTL, Assertain(TM) monitors, measures and manages the verification process in one integrated environment. The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test grading and optimization, linked to specification coverage using proven requirements traceability techniques.
Verification Closure Management
Verification Closure is achieved when a pre-defined level of confidence in the correctness of a design has been attained. Such confidence comes when the design team can prove that all design requirements has been implemented and verified.
Increasing circuits complexity, time-to-market, corner-case bugs - and more - all conspire to compound the verification problem. Project managers are forced to make a trade off between the level of verification achieved, time-to-market, and the risk of taping out a non-functional chip.
To overcome these issues, engineering teams had to multiply their verification resources and augment the verification time in an attempt to decrease the risk of an expensive re-spin. The main reason for this inefficiency is the lack of unified and accurate measures of verification quality and completeness.
TransEDA enhances control of the verification process
AssertainTM has been built around a revolutionary assertion coverage technology. Deploying comprehensive and unique assertion coverage metrics such as structural, step and variable coverage, TransEDAs solution enables precise measurements of how well assertions have been exercised by simulation, and how well they cover the intended behavior.
The cross-linked results from assertion coverage and code coverage are combined in a single, unified database that provides a clear view of how design verification is progressing.
Seamless mix of static and dynamic technologies
In addition to recording code and assertion coverage from dynamic simulation, TransEDA has embedded in AssertainTM its customer-proven formal engine, to be used transparently where formal algorithms are best suited to address a verification problem.
This engine augments the capabilities of the tools integrated rule checking with advanced formal verification of design consistency rules, such as bus contention and high impedance, FSM deadlock and livelock, array out-of-bound, etc. Formal technology is also used to automatically check protocol coverage and compliance with bus standards such as OCP, AHB and AXI.
Empowered by Coverability Analysis, and linked to initial specifications
Assertions which are not fully coverable not only slow down simulation, but may also appear to pass only because they are not reachable, thus giving engineers a false sense of security and increasing the risk of an re-spin.
TransEDA has integrated its unequaled Coverability Analysis technology into AssertainTM. Design Coverability Analysis can shave weeks off the verification time by applying formal techniques to identify areas where additional testing should be directed, filtering out those that are not reachable.
Assertion Coverability Analysis similarly provides an accurate measure of the effectiveness of PSL or SystemVerilog Assertions in a design.
However, verifying that the product is being built right is useless if one does not ensure that the right product is being built. AssertainTM provides a unique solution linking specification requirements, RTL, assertions and tests, to give engineers the ability to automatically track and verify that all original design requirements have been met and properly tested, therefore providing, for the first time, a specification coverage metric closely linking the specification, the RTL and test-benches via assertions.
An open and independent solution
Independent of platforms, languages, EDA vendor or verification tools, AssertainTM provides a single data point for the Assertion-Based Verification (ABV) approach.
GUI or command line interfaces combined with interactive or batch mode operations enable the tool to easily fit into any existing design flow. TransEDA users enjoy full backwards compatibility with existing TransEDA tools and results files allowing a smooth and seamless up-grade path.
The Logical Step to Verification Closure
For long, users have had to use a collection of separate verification tools, such as simulation, emulation, acceleration, pseudo-random testbench generation and formal verification. However, despite the current trend to integrate these point tools in platforms, they are still not working smoothly together, mainly due to the lack of common metrics to measure what these technologies really verify.
AssertainTM, TransEDAs new generation product represents a major advance in delivering a coherent and integrated verification closure solution. The results from specification coverage, assertion coverage, advanced code coverage, and coverability analysis are combined in a single, unified set of metrics and cross-linked together to provide a complete audit of your design as you progress towards a successful and faster tape-out. TransEDA is the only company to offer an open and independent solution for Verification Closure Management.
Pricing and Availability
AssertainTM is available on Solaris and Linux. Pricing starts from $30K for a perpetual license.
TransEDA will demonstrate this innovative new approach to design verification at the 42nd DAC (Design Automation Conference) June 13 17, 2005, in San Diego, CA.
About TransEDA
TransEDA is a leading provider of coverage and verification measurement solutions for electronic designs.
The company develops an advanced Verification Closure Management environment that takes advantage of both static and dynamic technologies to give engineers access to a unified view of the design verification progresses.
Unique functionalities such as comprehensive assertion coverage, coverability analysis, specification coverage with engineering change impact analysis, and automatic bus protocol checking, enhance the traditional code coverage, test suite optimization, HDL rule checking and static assertion checking capabilities to form an integrated Verification Closure Management solution.
Other products include verification IP with bus-based system-level test automation and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, plus local representatives in China, India, Korea, Singapore and Taiwan.
For more information, visit www.transeda.com.
TransEDA, the TransEDA logo and Verification from Concept to Reality are registered trademarks of TransEDA Technology Ltd.
All other trademarks are the property of their respective owners.
|
||||||
Related News
- TransEDA announces the first production release of Assertain, the next generation verification closure solution
- TVS adds web interface to its asureSIGN verification tool for real-time requirements management sign-off status
- Agnisys announces an innovative tool for Verification Management and Requirement Tracking
- Assertain success boosts investors' interest in TransEDA Assertion-Based Verification strategy
- TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite
Breaking News
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- TSMC Celebrates 30th North America Technology Symposium with Innovations Powering AI with Silicon Leadership
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
|
E-mail This Article | 
|
|
Printer-Friendly Page |