Meet the DSP Algorithmic Experts at DAC 2005; AccelChip Focuses on DSP Solutions in Booth 1000

MILPITAS, CA, May 31, 2005 – AccelChip Inc., the industry’s only provider of automated flows from MATLAB® algorithms to silicon, will demonstrate DSP solutions that enable language-based synthesis, architectural design exploration, and implementation of MATLAB algorithms in booth 1000 at the Design Automation Conference being held in Anaheim, California from June 13 to 16.  

Products on Display

• AccelChip DSP Synthesis – language-based algorithmic synthesis that accelerates the execution of MATLAB algorithms directly into FPGAs and ASICs by providing an automated path to implementation and verification of flows for DSP algorithms
• AccelWare DSP IP Core Generators – DSP toolkits for communications, signal processing, linear algebra, and building blocks
• AccelCore DSP RTL Cores – VHDL/Verilog, fixed-point linear algebra DSP cores that are fully validated in silicon and tailored to customer specifications

On-the-Floor Tutorials Provide Education on Solutions to Real World DSP Design Challenges
Four unique floor tutorials will explore solutions to challenges faced by DSP architects, systems designers and hardware designers as they move algorithms from concept to silicon implementation.  

1.    Implementing algorithms for sensor array processing using design methods based on MATLAB.  
The rapidly developing field of sensor array processing enables applications including radar, sonar, beamforming, GPS navigation, and multiple-input/multiple-output (MIMO) algorithms.  These applications require large amounts of adaptive processing, making implementation in cost-effective, fixed-point hardware the preferred choice.  However, implementation in these fabrics requires attention to finite-precision effects incurred with fixed-point arithmetic.  AccelChip experts will discuss the use of adaptive algorithms and will describe how to implement critical blocks of designs using linear algebra techniques with fixed-point arithmetic in FPGAs and ASICs.

2.    Unified path to verified Xilinx DSP FPGA systems using the industry’s only MATLAB/Simulink implementation solution.  
Custom DSP algorithms are best modeled mathematically using MATLAB, while complete systems are best modeled cycle-accurate using Simulink.  The marriage of these two modeling domains provides an efficient means of designing DSP systems into FPGAs by allowing the rich MATLAB language to create System Generator IP blocks of complex DSP algorithms.  Xilinx representatives will provide an overview of the integration between AccelChip DSP Synthesis and System Generator for DSP as an example of the most productive means to completing high quality designs in less time.

3.    Accelerating DSP algorithmic development on hardware evaluation platforms.  Developers face significant challenges when attempting to prototype complex algorithms in a timely fashion.  Hardware verification and hardware integration onto evaluation platforms is problematic and can be time consuming.  AccelChip experts will discuss a methodology that will allow developers to quickly and painlessly transition from algorithmic description using MATLAB onto a hardware evaluation platform.

4.    Implementing communications algorithms using design methods based on MATLAB.  
Emerging wireless standards and wireless technologies are requiring higher performance and more flexibility in their implementation.  While experienced software developers and system designers are familiar with software implementations of algorithms, they often struggle to adapt to the requirements of silicon implementation, including optimizing their design specification. In this session AccelChip experts will discuss how the use of algorithmic synthesis and parameterized IP can be effectively used to accelerate the development and implementation of these advanced systems.

AccelChip Sponsors Customer-focused Panel Discussion on ESL Solutions
Today’s SoCs are deploying increasingly computation-intensive algorithms that are implemented in dedicated hardware.  The need to rapidly and efficiently design from a high-level description to RTL has never been greater.  Recently, there have been debates on which language best suits the need to rapidly and efficiently design from a high-level description to RTL.   

AccelChip is sponsoring a discussion on electronic system level (ESL) design at the Anaheim Convention Center, Hall D, on Tuesday, June 14 from 11:30-12:15, entitled “ESL: Is it just MATLAB and Excel Spreadsheets?”  Participants include moderator Grant Martin with Tensilica, and participants Dr. Charles Le with JPL, Vili Tamas with Intel, and Maurizio Vitale with Philips.  The three panelists will discuss and debate the various methodologies that they employ in their real-world designs, the pros and cons of each approach, and their future needs from vendors of ESL solutions.

About the Company
AccelChip Inc. provides solutions for digital signal processing (DSP) design that enable customers to rapidly explore the architectural design space and implement algorithms in FPGAs and ASICs.  The company’s complete solutions include a comprehensive DSP design infrastructure, DSP intellectual property, and technology adoption services that invest in the transfer of knowledge to customers.  AccelChip’s proven solutions integrate the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx.  Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com.

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