Avery Design and ASIC Architect Team to Deliver PCI Express IP Solution

ANDOVER, Mass. -- June 10, 2005 -- Avery Design Systems and ASIC Architect today announced a cooperative effort to deliver a comprehensive PCI Express design and verification IP solution.

"Avery is excited to team with ASIC Architect to promote a cohesive design IP and core-to-chip-level verification solution for our customers," said Chilai Huang, president of Avery Design. "Working with IP vendors is a cornerstone in Avery's ability to continue to offer leading edge, comprehensive verification solutions. Our customers will benefit by ASIC Architect and Avery having shared goals and objectives on meeting their needs. Also from a solid core foundation, Avery has been able to build the innovative PCI Express chip and system level verification features that our customers have come to rely on."

"The complexity of PCI Express technology, now and then Gen2 going forward demands a very focused effort in order to provide a complete quality solution to our end customers. ASIC Architect focuses on developing high-quality PCI Express IP and solution. Avery's verification framework provides ASIC Architect a solid foundation to develop our PCI Express IP cores. With Avery we have been able to rapidly validate our cores using their compliance, error, and stress tests and go for compliance sign-off with confidence," said Kishore Mishra, president and CEO of ASIC Architect. "Our mutual customers know that their chip and system-level verification is streamlined by leveraging the same robust environment as their core provider."

Under the terms of the agreement, ASIC Architect and Avery will jointly promote their comprehensive solution to end users. Additionally, ASIC Architect has licensed Avery's PCI-Xactor solution to use for internal development.

About PCI-Xactor for PCI Express

The PCI-Xactor for PCI Express Verification Solution is a complete verification solution consisting of Bus Function Model (BFM), SuperMonitor, and test suites and verification frameworks for functional verification of PCI Express components. The PCI-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their PCI Express compliant devices. Verification frameworks form complete testbench environments for endpoint, switch, and bridge designs. Verification engineers just need to replace an Avery BFM with their design and begin running comprehensive verification tests. The PCI-Xactor environment leverages advanced verification techniques of Avery's TestWizard product supporting complex data structures, transaction database, random generation, temporal property checking, and coverage analysis.

Key Features

• Verilog source code format for BFMs and testcases
• Complete set of fully functional BFMs and testbenches for every PCI Express component: Endpoint, Root Complex, Switch, and PCI/PCI-X to PCI Express Bridge
• Support for serial, 10-bit symbol, and PIPE interfaces.
• Robust BFM API automates sending TLPs/DLLPs and controlling automatic BFM device response behaviors and link and device state transitions
• Supports transaction-oriented request-completion and error injection sequences based on address and command type attributes
• Inject errors and noise at all layers
• Root Complex provides BIOS enumeration functions to validate OS and PCI2.3 compatibility
• Test suites include the PCI-SIG-based compliance tests in addition to Avery-based endpoint, root complex, and switch testsuites that target high compliance coverage from their corresponding checklists
• Test are self-checking, portable, and reusable on most types of designs
• SuperMonitor verifies transaction ordering in N-port switch and bridge designs
• Native programming interfaces for Vera, Specman, SystemVerilog, SystemC, VHDL, C/C++

About ASIC Architect Cores

ASIC Architect offers a wide range of PCI Express Cores - Endpoint, Dual Mode - Root and Endpoint, Root Complex, Switch Port and related Solutions for ASIC and FPGA.

Key Features

• PCI Express Specification 1.0a or 1.1 Compliant
• Low Gate and Memory Count
• Low Transmit and Receive Latency
• Supports x8, x4, x2, x1 Lanes.
• Choice of 32/64/128 bit Datapath on Application Interface
• Choice of Single or Dual PIPE Mode on Phy Interface
• Technology Independent Design for ASIC, FPGA
• Excellent Support from Core Integration through Silicon Bring-up

About PCI Express technology

PCI Express technology is the new industry-standard I/O targeted to provide local connectivity across desktop, mobile, enterprise and communications platforms. PCI Express resides at the center of enterprise interconnect innovations anticipated across storage, networking, and clustering and workstations. Next-generation servers, utilizing PCI Express technology, will offer powerful and cost-effective computing platforms, scalable hardware building blocks, market-tested best-of-breed solutions, and enterprise-class reliability, availability, serviceability and manageability.

About Avery Design Systems

Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com.

About ASIC Architect

ASIC Architect, Inc. specializes in providing IP Cores, Solutions and Services in PCI Express and Advanced Switching for ASIC and FPGA. Additional information about ASIC Architect, Inc is available at http://www.asic-architect.com/

PCI-SIG, PCI Express, PCI, and PCI-X are either registered trademarks or trademarks of PCI-SIG in the United States and/or other countries. All other trademarks are the property of their respective owners.