Fremont, Calif. - While most of the attention in system-on-chip design remains focused on digital issues-IP selection, interconnect architecture, memory generation and the like-yet another kind of integration problem is quietly creeping up on designers, especially in compact, highly mobile applications. This one involves power-not power reduction, but power supply.

"Miniaturization is forcing system designers of very compact devices, like MP3 players, to consider moving voltage regulation onto the SoC," argued Mike Shamshirian, vice president of sales and business development at LTRIM Technology. "Not only is there no room left in the package for an external voltage regulator or dc/dc converter, but SoCs increasingly require multiple voltages. That increases the number of supply and ground pins and the susceptibility to noise coupling onto the those pins."

Other, more challenging issues are coming up as well. As designers increasingly turn to voltage islands and dynamic voltage/frequency scaling to reduce power consumption, the power needs of particular blocks on the SoC are becoming quite dynamic-so much so that it is a challenge to package and chip-routing resources to deliver rapid changes in current and voltage from an external pin to the block. This may force designers to integrate point-of-use regulators onto the die for some blocks. In addition, die-to-die process variations might require tuning the voltage to the characteristics of a particular die, maybe even at a particular operating temperature.

But voltage supplies are not within the normal range of IP. They are mixed-signal designs, often done in large-geometry processes with access to good analog transistors and safely kept on their own substrate to avoid noise or thermal coupling to the circuits they serve. And, especially in battery-supplied applications, they need to be as efficient as possible while tolerating a wide input voltage range. Not the kind of new block one undertakes to integrate lightly.

LTRIM is trying to change that perception. Last week, the company introduced a line of dc/dc converter IP blocks intended to be implemented in standard 3.3- or 1.8-volt logic processes in 0.25-, 0.18- or 0.13-micron logic processes. The designs use external passive components and only logic transistors, so they require no special process modules for the SoC.

Shamshirian said that there is almost no die area penalty for integrating such modules. "We are talking about maybe 0.4 mm2 in additional die area," he said.

Designs will first be available for TSMC's 0.18-micron processes, with 130-nanometer and quarter-micron versions to follow.