Tools missing as ESL rolls

Anaheim, Calif. — Soo-Kwan Eo had disconcerting news last week for anyone who's counting on electronic system-level design to be the catalyst for returning the EDA industry to growth. Eo, senior vice president at Samsung Electronics Co. Ltd., said that while Samsung's ESL resource allocation is increasing, its expenditure on commercial ESL tools is declining.

"We couldn't find the right tools," Eo said during a panel discussion here at the 42nd Design Automation Conference. So Samsung is working with universities and research institutes to develop its own, he said.

ESL appears at last to be making good on its promise — first proffered 10 years ago — to bring designers above the register-transfer level. Eo was one of several ESL users who reported at DAC that chip designers are starting to use system-level methodologies, particularly transaction-level modeling based on SystemC.

But that doesn't directly translate into EDA sales. While some designers reported using commercial ESL tools, others are rolling their own or are using open-source software available from Open SystemC International (OSCI). And all came to DAC with wish lists of capabilities that commercial tools have yet to meet.

The ESL field should provide plenty of opportunity. At the annual Gartner Dataquest briefing at DAC, chief analyst Daya Nadamuni predicted a surge in ESL revenues, from about $200 million today to $1.6 billion in 2009. At that point, ESL and RTL tool revenues would be roughly equivalent. "What will it take to drive [EDA] growth to double digits?" she asked. "It really seems like ESL is going to be the savior."

At the same briefing, however, Gartner Dataquest Inc. chief analyst Gary Smith noted that 27 percent of chip designers are now using internal tools, up from 20 percent in 2001. And the EE Times/Deutsche Bank 2005 EDA survey found that system-level design is a key area for internal tool development (see June 13, page 24).

ESL's challenges start with "defining what it is," said Emil Girczyc, CEO of Summit Design Inc., at a DAC panel session. Historically viewed as anything above RTL, what ESL really involves is highly application-dependent, he said.

"The ESL goal is concurrent hardware/software design from a single high-level model," said Dataquest's Nadamuni. Dataquest has identified three ESL methodologies: one for processors and memories, one for control logic and one for algorithms, each involving its own behavioral- and architectural-level tools and techniques.

The SystemC factor
ESL techniques such as C-language modeling, transaction-level modeling and algorithm development using Matlab have been around for years. What's different now is that SystemC is bringing high-level design techniques to designers who are stepping above RTL for the first time.

One of those is Tom Paulson, principal engineer at QLogic Corp., a developer of Fibre Channel switch ASICs. Just a year ago, Paulson wasn't even sure what ESL was. Since then his company has adopted SystemC modeling, along with analysis and graphical entry tools from Summit.

"Our RTL design flow is working very well," Paulson said. "But our algorithms are becoming more complex, and we wanted to look into architectural modeling."

After a successful evaluation that involved creating a SystemC model of an existing ASIC, QLogic brought SystemC modeling into its production design flow, where it's used to evaluate such features as buffer size, steering algorithms, transmit algorithms and service delivery.

The result is better design quality, Paulson said, but QLogic is taking it slow. "We're using the SystemC model to evaluate architectural features, but we're not looking at this point to move it to RTL."

Samsung has been at it a little longer and is getting closer to the Dataquest vision of concurrent hardware/software design. Samsung has been using SystemC transaction-level modeling since 2003. Last year, Eo said, the company set up a "virtual platform design methodology," with presilicon software development and verification, architectural exploration and performance analysis, and hardware/software co-verification.

Samsung is developing tools for embedded software optimization, low-power optimization and hardware/software co-design, and it is building links to external tools.

But Eo's list of ESL problem areas is long. It includes a lack of a measurable performance index to justify tool investments and the lack of equivalence checking. And "it takes so much effort to create the models that all the advantages ESL has could be wiped out by the modeling effort," he said.

Other designers are developing their own ESL strategies. Sriram Sundararajan, senior staff member at Texas Instruments Inc., called SystemC transaction-level models useful for architectural definition and validation, but he added that "tools are lacking in this area, which is the most important part of system design."

Using an internal approach along with open-source tools from OSCI, Sundararajan said, TI has developed high-level SystemC models that transfer tokens rather than data. "These models come up quickly, and even without RTL, we can get a lot of insights into the architecture," he said.

Qualcomm Inc. uses SystemC for architectural characterization, said principal engineer Suhas Pai. It also uses a "virtual platform" for IP modeling, a system-on-chip testbench for simulation and a transaction-level co-emulation approach.

SystemC modeling helps design become a more "concurrent" process and allows early architectural exploration, Pai said, but Qualcomm designers "really could have used training on how to use the language features for more efficient modeling, because the language is so rich."

Terry Doherty, principal engineer at Emulex Corp., has been doing system-level modeling for about three years. He uses SystemC transaction-level models for architectural analysis and exploration for the company's storage-networking chips.

With SystemC, Doherty can optimize buffer sizes, implement new protocols, make hardware/software trade-offs and ensure that FIFOs won't overflow. He uses commercial tools for analysis and debug but proprietary tools for analyzing protocols. His wish list includes tools to prove RTL code meets system requirements, along with better data management.

STMicroelectronics described a homegrown Matlab-to-RTL flow that was used to design a 135-Mbit/second, DVB-S2 complaint codec. The flow uses formal methods to verify the RTL against the high-level description. ST is also developing an automated synthesis flow, said Pascal Urard, signal processing senior expert.

There are a gaps in these flows, Urard noted, including synthesizable code generation from Matlab to SystemC, formal proof for the generated C and RTL code, and code checkers at many levels. The learning curve can be steep, he noted.

As for SystemC itself, Charles Pilkington, senior staff R&D engineer for SoC platform automation/central R&D at STMicroelectronics, would like enhanced simulation and debugging definitions.

"System C is good but not perfect," said Reinaldo Bergamaschi, research staff member for the System-Level Design Group at IBM's Thomas J. Watson Research Center. He called for more involvement of the "open development" community and for better links between SystemC methodologies and RTL flows.

EDA vendors respond
Earlier this month, the EDA vendor community rallied behind the SystemC transaction-level modeling (TLM) standard 1.0, which defines application programming interfaces and a library that implements a foundation layer on which interoperable transaction-level models can be built (see June 6, page 18).

One DAC forum involved ESL providers Summit, ChipVision Design Systems AG, Calypto Design Systems Inc., Critical Blue and Forte Design Systems Inc. Summit's Girczyc outlined an approach to ESL that is driven by application software rather than hardware.

Stan Krolikoski, CEO of ChipVision, presented his company's work with ESL power estimation. He said one customer had attained a 70 percent power savings.

Mike Meredith, vice president of technical marketing at Forte, claimed that six of the top 12 chip vendors use Forte's Cynthesizer SystemC tool and that 20 designs are in production with it.

Forte also took part in a novel benchmark at DAC. John Cooley, moderator of the E-Mail Synopsys Users Group, bet Forte VP Brett Cline that fewer than half of the respondents to Cooley's Design and Verification survey would say they planned to use SystemC in six months. The loser would have to don a chicken suit.

Cooley and Cline walked into a demo suite to review the survey results. Cline walked out wearing the feathers.

— Contributions by Nicolas Mokhoff