Frontier Design cores handle up to 6,250 channels

Frontier Design cores handle up to 6,250 channels
By Patrick Mannion, EE Times
November 1, 2000 (12:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001101S0048

SANTA CLARA, Calif. — Frontier Design has introduced four adaptive differential pulse code modulation (ADPCM) intellectual property cores that can handle up to 256 channels in a single Xilinx Virtex FPGA, or up to 6,250 channels in an ASIC implementation. The cores are designed to capitalize on the increasing use of ADPCM for voice-over-Internet Protocol, digital telephony, intercoms, telephone answering machines, and mass storage.

The four cores comprise two single- and two multi-channel cores that are available in either VHDL (IEEE1076-1987) or Verilog (IEEE 1364-1993) for optimized implementation in Xilinx Virtex XCV400E, XCV200E or XCV150 FPGAs, as well as for standard cell-based ASIC implementations. The ADPCM core is also available in a bit-true C-language implementation that can be parameterized for different applications.

The highly parallelized core was designed using the company's A/RT Builder C-to-HDL translation tool, which gene rated the single-cycle implementation. The cores are fully programmable for 16-, 24-, 32-, or 40-kbit/second operation, with programmable A-law, mu-law or linear coding of input or output. Both cores are fully compliant with ITU-recommended G.726 test vectors.

A 2.048-MHz clock on the FPGA implementation minimizes power operation. The 512-channel Virtex implementation requires 2,306 slices and 36 block RAMs, while the 256-channel Virtex implementation requires 2,020 slices and 18 block RAMs. The 128-channel Virtex implementation requires 1,800 slices, but only nine block RAMs.

The ASIC version needs a clock frequency of 8 kHz per channel, so 128 channels can be encoded or decoded with a 1.024-MHz clock. Each channel of ADPCM encoding and decoding requires 280 bits of dual-port memory. The ASIC implementation of the 256-channel core requires about 20,000 gates or 78 gates per channel, operating at 2.048 MHz Using a 0.18-micron process, a clock speed of about 12.5 MHz is attainable, and allows 1,562 c hannels to be implemented in the 20,000-gate core.

As a result, all 672 channels required for two DS3 lines can be implemented in 20,000 ASIC gates. With additional pipelining, the ADPCM ASIC core can handle the full 6,250 channels, which allows seven DS3 lines to be encoded/decoded in the core. Four additional pipeline stages would increase the gate count to 32,000. In addition, each encoding or decoding channel needs just a single clock cycle per sample.

First-use pricing ranges from $20,000 for the single-channel Virtex FPGA, to $40,000 for the multichannel ASIC.