 |
IPFlex to Introduce Industry-Leading Dynamically Reconfigurable Processor and C-Based Design Environment at Hot Chips 17 and HPEC 2005DAPDNA-2 and DAPDNA-FW II Expected to Dazzle Participants with Technological Innovation and Market Potential Tokyo, Japan – August 10, 2005 - Tomoyoshi Sato, co-founder, CTO and Vice President of IPFlex Inc., will present a paper on DAPDNA-2* dynamically reconfigurable processor** technology at Hot Chips 17 at Stanford University, an annual conference on high-performance chips on August 16th. Also IPFlex will present a paper on DAPDNA-FW II design tool at High Performance Embedded Computing 2005 Workshop at Massachusetts Institute of Technology’s Lincoln Laboratory on September 20th. DAPDNA-2, a dynamically reconfigurable processor with the capability of changing its hardware functionality by instantaneously changing its on-chip circuit configuration, has been chosen and embedded into products by forward-thinking companies in image processing, network security, communications, and academic researches in North American and Japan. Because of the unique and advanced features, IPFlex’s technology and products have been selected to be showcased at Hot Chips 17 at Stanford University and High Performance Embedded Computing (HPEC) 2005 at Massachusetts Institute of Technology’s Lincoln Laboratory in the coming two months. With a high international recognition, Hot Chips is an event catered for designers and architects of high-performance chips, software, and systems, featuring advanced topics on technologies and products, with presentations on up-to-the-minute developments. Sponsored by IEEE and organized by Stanford University and the University of California, Berkeley, the annual conference this year will be held from August 14 to August 16 at Memorial Auditorium at Stanford. The program committee evaluates submissions on the basis of device performance, degree of innovation, use of advanced technology, and potential market significance. IPFlex’s DAPDNA-2 dynamically reconfigurable processor provides unmatched flexibility and high performance, while lowering overall system costs. Tomoyoshi Sato will discuss how this industry-leading solution addresses the requirements of the complex system designs. In addition to the paper presentation, IPFlex will be showcasing its hardware demo on-site. The outline of presentation by IPFlex is as follows:
For further information about Hot Chips, please visit. http://www.hotchips.org/hc17/index.htm High Performance Embedded Computing (HPEC) 2005 Workshop offers an opportunity to discuss techniques, approaches, and ongoing developments with relevance to real-time embedded computing to U.S. government-funded researchers from academia, industry, and government. Sponsored by DARPA and hosted by MIT, the ninth annual HPEC workshop will be held on September 20 to September 22 at MIT’s Lincoln Laboratory in Lexington, MA under the theme “Will Software Save Moore's Law?” Likewise to Hot Chips, HPEC’s committee strictly evaluates submissions and approves presentations that are technologically significant. IPFlex’s DAPDNA-FW II design tool supporting DAPDNA-2 processor is a multiple function tool suite that aids application development, from algorithm creation to design verification. DAPDNA-FW II software allows software designers to develop device applications with little hardware design expertise by seamlessly integrating advanced C-based application designs into hardware. The presentation will focus on the advantages of C-based hardware design for dynamically reconfigurable hardware, benefiting from the features in DAPDNA-FW II. The outline of presentation by IPFlex is as follows:
About DAPDNA-2 Dynamically Reconfigurable Processor DAPDNA-2 is a dual-core processor, comprised of a high-performance RISC processor core, called the DAP, and the dynamically reconfigurable core, DNA, a two-dimensional array of 376 processing elements (PEs). DAPDNA-2 can change its hardware configuration to provide the optimal circuitry for an application on demand. This configuration change can take place not only when the system is designed, but also during operation, dynamically, in a single clock cycle***, to meet the instantaneous change in needs of applications implemented by the system. About DAPDNA-FW II Integrated Development Environment The DAPDNA-FW II Integrated Development Environment is a set of high-performance design tools that cover the entire process of application development for the DAPDNA dynamically reconfigurable processor, from algorithm design through debugging on the hardware. With the DNA Designer included in the IDE, a developer can drag-and-drop PEs to flexibly create dataflows in a GUI environment. Also available are Data Flow C compiler (developed by Celoxica) for C users and a set of tool to generate DNA code from MATLAB/Simulink, enabling a designer to leverage existing software assets. Terminology * DAPDNA: Digital Application Processor, Distributed Network Architecture ** Dynamically Reconfigurable Processor: A processor capable of changing chip circuitry dynamically *** a single clock cycle: One clock switching operation is possible by creating configuration information beforehand and storing in the background configuration banks. About IPFlex IPFlex Inc. is a fabless semiconductor company established in March 2000. IPFlex supplies high performance, multifunctional processors that are dynamically reconfigurable, and also provides development software, evaluation boards, and peripheral interface products for the processors. With its DAPDNA-2 dynamically reconfigurable processors and Software to Silicon-based DAPDNA-FW II Integrated Development Environment software, IPFlex provides solutions to shorten development cycle and to respond quickly to the changes in applications. IPFlex, DAPDNA, and Software-to-Silicon are registered trademarks of IPFlex in Japan. Other corporate and product names are the trademarks or registered trademarks of their respective owners.
|
| |||||||||||||||||||||||||||||||||
