SynTest Receives "Multiple-capture DFT system for scan-based integrated circuits" Patent for At-Speed Scan/BIST Invention
The patented invention is in general referred to as "staggered skewed-load" or "staggered launch-on-shift". It is a method for providing true at-speed testing for synchronous and asynchronous multi-clock, multi-frequency domains. The method provides ordered capture clocks to detect or locate faults within multiple clock domains and faults crossing clock domains in an integrated circuit during at-speed BIST or at-speed scan-testing.
The major benefit of this patented DFT scheme is the reduction in the number of ATPG patterns compared to the traditional one-hot DFT scheme for multi-clock, multi-frequency designs. The resultant compaction of 3x-10x translates directly into test cost savings.
About SynTest:
SynTest Technologies, Inc., established in 1990, develops IPs for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 20 US patents. The Company's products improve an electronic design's quality and reduce overall design and test costs. Various applications that use these IPs include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in China, Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.
|
Related News
- LogicVision Announces Production Release of Memory Built-In Self-Repair and ScanBurst At-Speed Scan Solution Integrated With Mentor Graphic's FastScan and TestKompress
- GBT Receives Patent Grant Notification Covering its Integrated Circuits Reliability Verification Analysis and Auto-Correction Technology
- GBT Filed a Non-Provisional Patent for Automatic Generation of Integrated Circuits Layout Blocks
- Cellnetrix offers secure embedded operating system for Cortus-based M2M and IoT integrated circuits
- Avery Design Systems Performs RTL At-Speed DFT Testability Analysis
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |