First-Time-Ever Demo of FPGA Processing on a Serial RapidIO Device

CHATSWORTH, Calif.--Oct. 19, 2005--On October 25 and 26, 2005, at the GSPx conference in Santa Clara, Calif., Micro Memory(TM) will be performing a technology demonstration based on its CoSine System-on-Chip, the device selected as an "Ultimate Product" finalist by "EE Times." This demonstration will showcase for the first-time-ever, a Serial RapidIO device performing FPGA processing.

The demonstration will include full memory-to-memory transfers over a Serial RapidIO x4 backplane between CoSine and an endpoint from Mercury Computers.

CoSine will also be performing transforms on data utilizing a Xilinx® LogicCore(TM) 1024 point FFT, with 16-bit fixed point complex operations. Data will be sourced from a PCI-X device, displaying CoSine's seamless bus-bridging capabilities to RapidIO, and utilize QDR memory to perform the real time transforms before CoSine DMAs the data over the Serial RapidIO fabric to a Mercury Computers' endpoint.

This demonstration will signify a significant step for both the RapidIO community and utilizing FPGAs for DSP processing as it will be the first time a Serial RapidIO device will have performed FPGA processing. The product demonstration can be seen at Micro Memory's booth, #513, in the Exhibition Hall on Tuesday and Wednesday, October 25 and 26.

Held at the Santa Clara Convention Center on October 24 to 27, the GSPx conference is one of the industry's preeminent events specifically focused on high speed signal processing.

What is CoSine?

Micro Memory's CoSine device is the first fully integrated and preconfigured System-on-Chip for real time FPGA processing. CoSine efficiently bridges two high speed ports (PCI-X®, PCI-Express® or Serial RapidIO) through a large, multi-ported DDR controller. The device also includes a dedicated User Programmable Logic (UPL) block carved out from the rest of the device for application specific state machines and functions as FFTs or FIR filters.

Similar to a structured or platform ASIC, CoSine's IP cores, memory controllers, specialized DMA engines, embedded processors and surrounding logic are factory preconfigured and supplied as a fully tested system. This provides users the ability to focus on application specific state machine processing in the UPL block without concerning themselves with coding other modules, complicated SoC integration or verification. By providing a fully functional and verified solution, developers are given the opportunity to complete their custom logic and software in a complex SoC design faster than any other alternative approach.

Based on the leading Xilinx Virtex-II Pro and Virtex-4 FX families of FPGAs, each of CoSine's embedded PowerPCs are fully functional computers, each with its own DDR memory, Flash, UART and shared Ethernet. Each processor also includes its own Board Support Package and is capable of downloading files or running applications out of the box.

Technical Details of the Demonstration

Demo System Configuration

The demo will be based on a Serial RapidIO x4 ATCA® system. The CoSine SoC FPGA is located on Micro Memory's MM-333D ATCA carrier board. A processor PCI mezzanine card (PrPMC), the Xpedite1000 from Extreme Engineering® Solutions, resides on a MM-333D mezzanine site and communicates to CoSine via a 64-bit/133MHz PCI-X bus.

The Ensemble(TM) Serial RapidIO x4 system from Mercury Computers serves as the ATCA chassis for the demonstration. The MM-333D board resides in the Ensemble ATCA chassis, and an Ensemble Serial RapidIO x4 ATCA carrier board is also utilized in the demo with a PowerPC(TM) mezzanine from GDA® Technologies.

An off-the-shelf, Xilinx LogiCore 1024 point FFT is installed in CoSine's User Programmable Logic (UPL) block.

Data Transfer Setup

Residing on the MM-333D and serving as the data source, the Xpedite1000 processor mezzanine card utilizes a 440GX PowerPC and runs Windriver's® VxWorks® Tornado® 2.2 operating system.

• Signals generated by the Xpedite PMC are DMA'd over the PCI-X bus from the PMC to the CoSine FPGA SoC.
• CoSine's DMA engine transfers the data to CoSine's UPL block.
• CoSine's UPL first buffers the data in 36MB of Quad Data Rate (QDR) II SRAM.
• CoSine's UPL then reads data from the buffer, applies the FFT and outputs the results back to the DMA engine.
• The CoSine DMA engine then continues the original DMA transfer by storing the results in commanded location in CoSine's primary multi-ported DDR memory.
• The data is then read using CoSine's DMA engine from CoSine's primary DDR over the Serial RapidIO x4 backplane by a MPC8540 PowerPC on the RMC-G8500 RapidIO mezzanine card from GDA Technologies that runs Linux and resides on the Ensemble ATCA carrier board.

Execution of Data Transfers

With CoSine's UPL initialized to perform forward FFTs and set up to start automatically, the Xpedite1000 demo program is initiated and, in an endless loop, prompts the user, via a serial console, for an input frequency to be processed by the UPL. The frequency units are in cycles-per-1024 points.

Each user entry on the Xpedite1000 console causes a 1024-point 16-bit pure tone to be created in memory which is then sent to the UPL where a fixed-point FFT is performed on the data. The sine wave generated by the Xpedite is transferred via DMA directly to the UPL over the PCI-X 133 MHz interface. The XPedite requests the DMA transfer which is mastered by CoSine. CoSine UPL uses QDR for a FIFO buffer, performs the FFT and stores the final result in DDR.

Meanwhile, on the RMC-G8500 serial console, a demo program is initiated that periodically reads the data from primary DDR over the sRIO interface and displays the frequency bin corresponding to the peak in the FFT'd data. CoSine's Serial RapidIO DMA then transfers data over the Serial RapidIO backplane at the request of the RMC.

The result is that as soon as a frequency is entered on the Xpedite, the frequency is displayed on the RMC. In between, the data has been seamlessly moved from PCI-X to Serial RapidIO while performing a 1024-point FFT.

About Micro Memory

Micro Memory is a leading provider of board-level products for streaming signal and image processing, real-time data acquisition and enterprise network storage. Headquartered in Chatsworth, Calif., the company's innovative products solve challenging problems for industry-leading OEMs and system solution providers. Additional information is available at www.micromemory.com.