Alchemy taps Infineon for Carmel DSP cores

Alchemy taps Infineon for Carmel DSP cores
By Stephan Ohr, EE Times
September 26, 2000 (6:26 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000926S0087

SAN JOSE, Calif. — Infineon Technologies AG has licensed its Carmel DSP architecture to Alchemy Semiconductor Inc., an Austin, Texas-based startup.

Eric Broockman, Alchemy's president and chief executive officer, said the company will pair the Carmel 10xx and Carmel 20xx DSP cores with a MIPS RISC core to produce a custom device for its Internet Edge applications.

The convergence of voice and data communications — with xDSL and voice-over-Internet Protocol as the leading examples — demands high-performance DSP cores with low power consumption, Broockman said. The loose coupling of a MIPS core with the Carmel 2000, a 4-MAC version of Carmel's VLIW machine, provides an engine capable of up to 800 million multiply-accumulates per second, he said.

Infineon's version of the very long instruction word (VLIW) architecture — an architecture that parallelizes instructions to exercise a battery of parallel execution units on the sa me cycle — is based on a 144-bit instruction word. But up to 96 bits of this word can reflect a collapsible-or-expandable set of user-developed instructions, an architecture Infineon calls a configurable long instruction word (CLIW). While Alchemy has no plans for CLIW instructions, it is possible customers will use it in their implementations of the Alchemy chip in an Internet appliance.

Carmel was selected after the company had also evaluated TI and StarCore products, Broockman said. Many of these products were geared toward channel processing in basestation applications, while Alchemy wanted something more tuned to portable handsets, he said.